PIC18LF25K22-I/SS Microchip Technology, PIC18LF25K22-I/SS Datasheet - Page 169
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18LF25K22-I/SS
Manufacturer Part Number
PIC18LF25K22-I/SS
Description
MCU 8BIT 32KB FLASH 3.6V 28SSOP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18LF25K22-I/SS
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 19x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
256Byte
Ram Memory Size
1536Byte
Cpu Speed
64MHz
No. Of Timers
7
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1536 B
Interface Type
I2C, SPI, EUSART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
25
Number Of Timers
7
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 17 Channel
On-chip Dac
5 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF25K22-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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FIGURE 12-7:
12.12 Peripheral Module Disable
When a peripheral module is not used or inactive, the
module can be disabled by setting the Module Disable
bit in the PMD registers. This will reduce power con-
sumption to an absolute minimum. Setting the PMD
bits holds the module in Reset and disconnects the
module’s clock source. The Module Disable bits for
Timer1 (TMR1MD), Timer3 (TMR3MD) and Timer5
(TMR5MD) are in the PMD0 Register. See
“Power-Managed Modes”
2010 Microchip Technology Inc.
TIMER1/3/5
TMRxGIF
TMRxGE
TxGSPM
TxGPOL
TxGVAL
TxGGO/
TxG_IN
TxGTM
DONE
TxCKI
TIMER1/3/5 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE
Cleared by software
N
for more information.
Counting enabled on
rising edge of TxG
Set by software
Section 3.0
Preliminary
N + 1
falling edge of TxGVAL
Set by hardware on
N + 2
PIC18(L)F2X/4XK22
N + 3
N + 4
Cleared by hardware on
falling edge of TxGVAL
DS41412D-page 169
Cleared by
software
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