ATTINY24-15SSZ Atmel, ATTINY24-15SSZ Datasheet - Page 54

MCU AVR 2K FLASH 15MHZ 14-SOIC

ATTINY24-15SSZ

Manufacturer Part Number
ATTINY24-15SSZ
Description
MCU AVR 2K FLASH 15MHZ 14-SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet

Specifications of ATTINY24-15SSZ

Package / Case
14-SOIC (3.9mm Width), 14-SOL
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
16MHz
Number Of I /o
12
Eeprom Size
128 x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
128 x 8
Program Memory Size
2KB (2K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Connectivity
USI
Core Size
8-Bit
Cpu Family
ATtiny
Device Core
AVR
Device Core Size
8b
Frequency (max)
16MHz
Interface Type
SPI/UART
Total Internal Ram Size
128Byte
# I/os (max)
12
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
14
Package Type
SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY24-15SSZ
Manufacturer:
ATMEL
Quantity:
349
Part Number:
ATTINY24-15SSZ
Manufacturer:
ATTINY
Quantity:
20 000
11.2.5
54
Atmel ATtiny24/44/84 [Preliminary]
PCMSK0 – Pin Change Mask Register 0
• Bits 3..0 – PCINT11..8: Pin Change Enable Mask 11..8
Each PCINT11..8 bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT11..8 is set (logical one) and the PCIE1 bit in GIMSK is set, pin change interrupt
is enabled on the corresponding I/O pin. If PCINT11..8 is cleared, pin change interrupt on the
corresponding I/O pin is disabled.
• Bits 7..0 – PCINT7..0: Pin Change Enable Mask 7..0
Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT7..0 is set (logical one) and the PCIE0 bit in GIMSK is set, pin change interrupt is
enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the cor-
responding I/O pin is disabled.
Bit
0x12 (0x32)
Read/Write
Initial Value
PCINT7
R/W
7
0
PCINT6
R/W
6
0
PCINT5
R/W
5
0
PCINT4
R/W
4
0
PCINT3
R/W
3
0
PCINT2
R/W
2
0
PCINT1
R/W
1
0
PCINT0
R/W
0
0
7701D–AVR–09/10
PCMSK0

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