PIC18F1320-E/SS Microchip Technology, PIC18F1320-E/SS Datasheet - Page 67

• Manufacturer Part Number: PIC18F1320-E/SS
• Description: IC MCU FLASH 4KX16 EEPROM 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F1320-E/SS

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 20-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 7 bit
• Package: 20SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

EXAMPLE 6-3:
6.5.2
Depending on the application, good programming
practice may dictate that the value written to the mem-
ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
6.5.3
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed. The WRERR bit is set when a
write operation is interrupted by a MCLR Reset, or a
WDT Time-out Reset during normal operation. In these
situations, users can check the WRERR bit and rewrite
the location.
TABLE 6-2:
 2004 Microchip Technology Inc.
TBLPTRU
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>)
TABLAT
INTCON
EECON2
EECON1
IPR2
PIR2
PIE2
Legend:
WRITE_WORD_TO_HREGS
PROGRAM_MEMORY
Name
Program Memory Table Latch
GIE/GIEH PEIE/GIEL TMR0IE
EEPROM Control Register 2 (not a physical register)
x = unknown, u = unchanged, – = unimplemented, read as ‘0’.
Shaded cells are not used during Flash/EEPROM access.
WRITE VERIFY
UNEXPECTED TERMINATION OF
WRITE OPERATION
OSCFIP
OSCFIF
OSCFIE
EEPGD
Bit 7
—
MOVF
MOVWF
TBLWT+*
DECFSZ COUNTER
GOTO
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
BSF
DECFSZ COUNTER_HI
GOTO PROGRAM_LOOP
BCF
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
CFGS
POSTINC0, W
TABLAT
WRITE_WORD_TO_HREGS
INTCON, GIE
55h
EECON2
AAh
EECON2
EECON1, WR
INTCON, GIE
EECON1, WREN
Bit 6
—
—
—
—
bit 21
Bit 5
—
—
—
—
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 --00 0000
FREE
INTE
EEIP
EEIE
Bit 4
EEIF
WRERR
RBIE
Bit 3
—
—
—
; get low byte of buffer data and increment FSR0
; present data to table latch
; short write
; to internal TBLWT holding register, increment
; loop until buffers are full
; disable interrupts
; required sequence
; write 55H
; write AAH
; start program (CPU stall)
; re-enable interrupts
; loop until done
; disable write to memory
TBLPTR
TMR0IF
WREN
6.6
See Section 19.0 “Special Features of the CPU” for
details on code protection of Flash program memory.
LVDIP
LVDIF
LVDIE
Bit 2
Flash Program Operation During
Code Protection
PIC18F1220/1320
TMR3IP
TMR3IF
TMR3IE
INTF
Bit 1
WR
RBIF
Bit 0
RD
—
—
—
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 000x 0000 000u
xx-0 x000 uu-0 u000
1--1 -11- 1--1 -11-
0--0 -00- 0--0 -00-
0--0 -00- 0--0 -00-
POR, BOR
Value on:
—
DS39605C-page 65
Value on
all other
Resets
—