PIC18F45J10-E/ML Microchip Technology, PIC18F45J10-E/ML Datasheet - Page 79
![IC PIC MCU FLASH 16KX16 44QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18F45J10-E/ML
Manufacturer Part Number
PIC18F45J10-E/ML
Description
IC PIC MCU FLASH 16KX16 44QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F24J10-ISO.pdf
(368 pages)
3.PIC18F24J10-ISO.pdf
(6 pages)
4.PIC18F24J10-ISO.pdf
(6 pages)
5.PIC18F24J10-ISO.pdf
(12 pages)
6.PIC18LF24J10-ISS.pdf
(32 pages)
Specifications of PIC18F45J10-E/ML
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
For Use With
AC164336 - MODULE SOCKET FOR PM3 28/44QFNAC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180013 - MODULE PLUG-IN 18F45J10 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- PIC16F616T-ISL PDF datasheet
- PIC18F24J10-ISO PDF datasheet #2
- PIC18F24J10-ISO PDF datasheet #3
- PIC18F24J10-ISO PDF datasheet #4
- PIC18F24J10-ISO PDF datasheet #5
- PIC18LF24J10-ISS PDF datasheet #6
- Current page: 79 of 368
- Download datasheet (6Mb)
7.5
The minimum programming block is 32 words or
64 bytes. Word or byte programming is not supported.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are 64 holding registers used by the table writes for
programming.
Since the Table Latch (TABLAT) is only a single byte, the
TBLWT instruction may need to be executed 64 times for
each programming operation. All of the table write
operations will essentially be short writes because only
the holding registers are written. At the end of updating
the 64 holding registers, the EECON1 register must be
written to in order to start the programming operation
with a long write.
The long write is necessary for programming the inter-
nal Flash. Instruction execution is halted while in a long
write cycle. The long write will be terminated by the
internal programming timer.
FIGURE 7-5:
7.5.1
The sequence of events for programming an internal
program memory location should be:
1.
2.
3.
4.
© 2009 Microchip Technology Inc.
TBLPTR = xxxxx0
If the section of program memory to be written to
has been programmed previously, then the
memory will need to be erased before the write
occurs (see Section 7.4.1 “Flash Program
Memory Erase Sequence”).
Write the 64 bytes into the holding registers with
auto-increment.
Set the EECON1 register for the write operation:
• set WREN to enable byte writes.
Disable interrupts.
Writing to Flash Program Memory
FLASH PROGRAM MEMORY WRITE
SEQUENCE
Holding Register
8
TABLE WRITES TO FLASH PROGRAM MEMORY
TBLPTR = xxxxx1
Holding Register
8
Program Memory
TBLPTR = xxxxx2
Write Register
TABLAT
PIC18F45J10 FAMILY
The EEPROM on-chip timer controls the write time.
The write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
5.
6.
7.
8.
9.
10. Verify the memory (table read).
An example of the required code is shown in
Example 7-3.
Holding Register
Note:
Note:
Write 55h to EECON2.
Write 0AAh to EECON2.
Set the WR bit. This will begin the write cycle.
The CPU will stall for duration of the write (about
2 ms using internal timer).
Re-enable interrupts.
8
Unlike previous devices, the PIC18F45J10
family of devices does not reset the holding
registers after a write occurs. The holding
registers must be cleared or overwritten
before a programming sequence.
In order to maintain the endurance of the
cells, each Flash byte should not be
programmed more then twice between
erase operations. Either a Bulk or Row
Erase of the target row is required before
attempting to modify the contents a third
time.
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the 64 bytes in
the holding register.
TBLPTR = xxxx3F
Holding Register
DS39682E-page 77
8
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