PIC18F45J10-E/ML Microchip Technology, PIC18F45J10-E/ML Datasheet - Page 179
![IC PIC MCU FLASH 16KX16 44QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18F45J10-E/ML
Manufacturer Part Number
PIC18F45J10-E/ML
Description
IC PIC MCU FLASH 16KX16 44QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F24J10-ISO.pdf
(368 pages)
3.PIC18F24J10-ISO.pdf
(6 pages)
4.PIC18F24J10-ISO.pdf
(6 pages)
5.PIC18F24J10-ISO.pdf
(12 pages)
6.PIC18LF24J10-ISS.pdf
(32 pages)
Specifications of PIC18F45J10-E/ML
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
For Use With
AC164336 - MODULE SOCKET FOR PM3 28/44QFNAC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180013 - MODULE PLUG-IN 18F45J10 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- PIC16F616T-ISL PDF datasheet
- PIC18F24J10-ISO PDF datasheet #2
- PIC18F24J10-ISO PDF datasheet #3
- PIC18F24J10-ISO PDF datasheet #4
- PIC18F24J10-ISO PDF datasheet #5
- PIC18LF24J10-ISS PDF datasheet #6
- Current page: 179 of 368
- Download datasheet (6Mb)
16.4.6.1
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I
not be released.
In Master Transmitter mode, serial data is output
through SDAx, while SCLx outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ‘0’. Serial data is
transmitted 8 bits at a time. After each byte is transmit-
ted, an Acknowledge bit is received. Start and Stop
conditions are output to indicate the beginning and the
end of a serial transfer.
In Master Receive mode, the first byte transmitted
contains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate the receive bit.
Serial data is received via SDAx, while SCLx outputs
the serial clock. Serial data is received 8 bits at a time.
After each byte is received, an Acknowledge bit is
transmitted. Start and Stop conditions indicate the
beginning and end of transmission.
The Baud Rate Generator used for the SPI mode
operation is used to set the SCLx clock frequency for
either 100 kHz, 400 kHz or 1 MHz I
Section 16.4.7 “Baud Rate” for more detail.
© 2009 Microchip Technology Inc.
I
2
C Master Mode Operation
2
C operation. See
2
C bus will
PIC18F45J10 FAMILY
A typical transmit sequence would go as follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. The MSSP module generates an interrupt at the
11. The user generates a Stop condition by setting
12. Interrupt is generated once the Stop condition is
The user generates a Start condition by setting
the Start Enable bit, SEN (SSPxCON2<0>).
SSPxIF is set. The MSSP module will wait the
required start time before any other operation
takes place.
The user loads the SSPxBUF with the slave
address to transmit.
Address is shifted out the SDAx pin until all 8 bits
are transmitted.
The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPxCON2 register (SSPxCON2<6>).
The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the
SSPxIF bit.
The user loads the SSPxBUF with eight bits of
data.
Data is shifted out the SDAx pin until all 8 bits
are transmitted.
The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPxCON2 register (SSPxCON2<6>).
end of the ninth clock cycle by setting the
SSPxIF bit.
the Stop Enable bit, PEN (SSPxCON2<2>).
complete.
DS39682E-page 177
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