ATMEGA16A-MUR Atmel, ATMEGA16A-MUR Datasheet - Page 19

• Manufacturer Part Number: ATMEGA16A-MUR
• Description: MCU AVR 16KB FLASH 16MHZ 44QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16A-MUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.4.3
7.5
7.6
7.6.1
8154B–AVR–07/09
I/O Memory
Register Description
Preventing EEPROM Corruption
EEARH and EEARL – The EEPROM Address Register
as a consequence, the device does not enter Power-down entirely. It is therefore recommended
to verify that the EEPROM write operation is completed before entering Power-down.
During periods of low V
too low for the CPU and the EEPROM to operate properly. These issues are the same as for
board level systems using EEPROM, and the same design solutions should be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too low. First,
a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Sec-
ondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.
EEPROM data corruption can easily be avoided by following this design recommendation:
The I/O space definition of the ATmega16A is shown in
All ATmega16A I/Os and peripherals are placed in the I/O space. The I/O locations are
accessed by the IN and OUT instructions, transferring data between the 32 general purpose
working registers and the I/O space. I/O Registers within the address range $00 - $1F are
directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single
bits can be checked by using the SBIS and SBIC instructions. Refer to the Instruction Set sec-
tion for more details. When using the I/O specific commands IN and OUT, the I/O addresses $00
- $3F must be used. When addressing I/O Registers as data space using LD and ST instruc-
tions, $20 must be added to these addresses.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI
instructions will operate on all bits in the I/O Register, writing a one back into any flag read as
set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only.
The I/O and Peripherals Control Registers are explained in later sections.
Bit
Read/Write
Initial Value
Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This
can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the
internal BOD does not match the needed detection level, an external low V
tion circuit can be used. If a reset occurs while a write operation is in progress, the write
operation will be completed provided that the power supply voltage is sufficient.
EEAR7
R/W
15
R
X
–
7
0
CC,
EEAR6
R/W
14
R
X
–
6
0
the EEPROM data can be corrupted because the supply voltage is
EEAR5
R/W
13
R
X
–
5
0
EEAR4
R/W
12
R
X
–
4
0
EEAR3
R/W
11
R
X
–
3
0
“Register Summary” on page
EEAR2
R/W
10
R
X
–
2
0
EEAR1
R/W
R
X
9
–
1
0
ATmega16A
EEAR8
EEAR0
CC
R/W
R/W
X
X
8
0
Reset Protec-
334.
EEARH
EEARL
19