ATTINY261-15MZ Atmel, ATTINY261-15MZ Datasheet - Page 74

• Manufacturer Part Number: ATTINY261-15MZ
• Description: MCU AVR 2K FLASH 15MHZ 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY261-15MZ

• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 16
• Eeprom Size: 128 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Program Memory Size: 2KB (2K x 8)
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.2.2
14.3
14.4
74
Timer/Counter Clock Sources
Counter Unit
ATtiny261/ATtiny461/ATtiny861
Definitions
OCR0A contains the low byte of the word and OCR0B contains the high byte of the word. When
accessing 16-bit registers, special procedures described in section
16-bit Mode” on page 81
Many register and bit references in this section are written in general form. A lower case “n”
replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com-
pare Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or
bit defines in a program, the precise form must be used, i.e., TCNT0L for accessing
Timer/Counter0 counter value and so on.
The definitions in
Table 14-1.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the T0 pin. The Clock Select logic is controlled by the Clock Select (CS02:0) bits located in the
Timer/Counter Control Register 0 B (TCCR0B), and controls which clock source and edge the
Timer/Counter uses to increment its value. The Timer/Counter is inactive when no clock source
is selected. The output from the Clock Select logic is referred to as the timer clock (clk
details on clock sources and prescaler, see
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
14-3
Table 14-2.
Signal description (internal signals):
BOTTOM
MAX
TOP
shows a block diagram of the counter and its surroundings.
count
clk
top
Tn
The counter reaches the BOTTOM when it becomes 0.
The counter reaches its MAXimum when it becomes 0xFF (decimal 255) in 8-bit mode or
0xFFFF (decimal 65535) in 16-bit mode.
The counter reaches the TOP when it becomes equal to the highest value in the count
sequence. The TOP value can be assigned to be the fixed value 0xFF/0xFFFF (MAX) or the
value stored in the OCR0A Register.
DATA BUS
Definitions
Counter Unit Block Diagram
TCNTn
Table 14-1
must be followed.
are also used extensively throughout the document.
Increment or decrement TCNT0 by 1.
Timer/Counter clock, referred to as clk
Signalize that TCNT0 has reached maximum value.
count
Control Logic
“Timer/Counter0 Prescaler” on page
top
TOVn
(Int.Req.)
clk
Tn
Clock Select
( From Prescaler )
Detector
Edge
T0
“Accessing Registers in
in the following.
70.
7753F–AVR–01/11
Tn
T0
Figure
). For