ATTINY261-15MZ Atmel, ATTINY261-15MZ Datasheet - Page 124

• Manufacturer Part Number: ATTINY261-15MZ
• Description: MCU AVR 2K FLASH 15MHZ 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY261-15MZ

• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 16
• Eeprom Size: 128 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Program Memory Size: 2KB (2K x 8)
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.11.8
16.11.9
16.11.10 OCR1C – Timer/Counter1 Output Compare Register C
124
ATtiny261/ATtiny461/ATtiny861
OCR1A – Timer/Counter1 Output Compare Register A
OCR1B – Timer/Counter1 Output Compare Register B
The output compare register A is an 8-bit read/write register.
The Timer/Counter Output Compare Register A contains data to be continuously compared with
Timer/Counter1. Actions on compare matches are specified in TCCR1A. A compare match does
only occur if Timer/Counter1 counts to the OCR1A value. A software write that sets TCNT1 and
OCR1A to the same value does not generate a compare match.
A compare match will set the compare interrupt flag OCF1A after a synchronization delay follow-
ing the compare event.
Note that, if 10-bit accuracy is used special procedures must be followed when accessing the
internal 10-bit Output Compare Registers via the 8-bit AVR data bus. These procedures are
described in section
The output compare register B is an 8-bit read/write register.
The Timer/Counter Output Compare Register B contains data to be continuously compared with
Timer/Counter1. Actions on compare matches are specified in TCCR1. A compare match does
only occur if Timer/Counter1 counts to the OCR1B value. A software write that sets TCNT1 and
OCR1B to the same value does not generate a compare match.
A compare match will set the compare interrupt flag OCF1B after a synchronization delay follow-
ing the compare event.
Note that, if 10-bit accuracy is used special procedures must be followed when accessing the
internal 10-bit Output Compare Registers via the 8-bit AVR data bus. These procedures are
described in section
The output compare register C is an 8-bit read/write register.
The Timer/Counter Output Compare Register C contains data to be continuously compared with
Timer/Counter1, and a compare match will clear TCNT1. This register has the same function in
Normal mode and PWM modes.
Bit
0x2D (0x4D)
Read/Write
Initial value
Bit
0x2C (0x4C)
Read/Write
Initial value
Bit
0x2B (0x4B)
Read/Write
Initial value
MSB
MSB
MSB
R/W
R/W
R/W
7
0
7
0
7
1
“Accessing 10-Bit Registers” on page
“Accessing 10-Bit Registers” on page
R/W
R/W
R/W
6
0
6
0
6
1
R/W
R/W
R/W
5
0
5
0
5
1
R/W
R/W
R/W
4
0
4
0
4
1
R/W
R/W
R/W
3
0
3
0
3
1
112.
112.
R/W
R/W
R/W
2
0
2
0
2
1
R/W
R/W
R/W
1
0
1
0
1
1
LSB
LSB
LSB
R/W
R/W
R/W
0
0
0
0
0
1
7753F–AVR–01/11
OCR1A
OCR1B
OCR1C