PIC18LF13K22-I/ML Microchip Technology, PIC18LF13K22-I/ML Datasheet - Page 155
PIC18LF13K22-I/ML
Manufacturer Part Number
PIC18LF13K22-I/ML
Description
IC PIC MCU FLASH 256KX8 20-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF13K22-ISS.pdf
(388 pages)
2.PIC18LF13K22-ISS.pdf
(12 pages)
3.PIC18LF13K22-ISS.pdf
(36 pages)
4.PIC18LF14K22-IP.pdf
(382 pages)
Specifications of PIC18LF13K22-I/ML
Program Memory Type
FLASH
Program Memory Size
8KB (4K x 16)
Package / Case
20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, MSSP, SPI, USART
Maximum Clock Frequency
32 KHz
Number Of Programmable I/os
18
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF13K22-I/ML
Manufacturer:
CAVIUM
Quantity:
155
- PIC18LF13K22-ISS PDF datasheet
- PIC18LF13K22-ISS PDF datasheet #2
- PIC18LF13K22-ISS PDF datasheet #3
- PIC18LF14K22-IP PDF datasheet #4
- Current page: 155 of 382
- Download datasheet (6Mb)
14.3.4.5
When the CKP bit is cleared, the SCL output is forced
to ‘0’. However, clearing the CKP bit will not assert the
SCL output low until the SCL output is already sam-
pled low. Therefore, the CKP bit will not assert the
SCL line until an external I
already asserted the SCL line. The SCL output will
remain low until the CKP bit is set and all other
devices on the I
ensures that a write to the CKP bit will not violate the
minimum high time requirement for SCL (see
Figure 14-12).
FIGURE 14-12:
© 2009 Microchip Technology Inc.
WR
SSPCON1
SDA
SCL
CKP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Clock Synchronization and
the CKP bit
2
C bus have deasserted SCL. This
CLOCK SYNCHRONIZATION TIMING
2
C master device has
DX
Master device
asserts clock
Preliminary
PIC18F1XK22/LF1XK22
Master device
deasserts clock
DS41365C-page 155
DX – 1
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