PIC12CE674-10I/P Microchip Technology, PIC12CE674-10I/P Datasheet - Page 594
PIC12CE674-10I/P
Manufacturer Part Number
PIC12CE674-10I/P
Description
IC MCU OTP 2KX14 A/D&EE 8DIP
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12CE673-10P.pdf
(129 pages)
3.PIC12CE673-10P.pdf
(3 pages)
4.PIC12CE673-10P.pdf
(14 pages)
5.PIC12CE673-10P.pdf
(12 pages)
Specifications of PIC12CE674-10I/P
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Eeprom Size
16 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12CE674-10I/P
Manufacturer:
MICROCHIP
Quantity:
12 000
- PIC16F688T-ISL PDF datasheet
- PIC12CE673-10P PDF datasheet #2
- PIC12CE673-10P PDF datasheet #3
- PIC12CE673-10P PDF datasheet #4
- PIC12CE673-10P PDF datasheet #5
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PICmicro MID-RANGE MCU FAMILY
Figure 30-10: Example SPI Master Mode Timing (CKE = 1)
Table 30-22:
DS31030A-page 30-24
Param.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
No.
71A
72A
73A
71
72
73
74
75
76
78
79
80
81
(CKP = 0)
(CKP = 1)
SDI
SS
SCK
SCK
SDO
† Data in “Typ” column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
TscH
TscL
TdiV2scH,
TdiV2scL
T
TscH2diL,
TscL2diL
TdoR
TdoF
TscR
TscF
TscH2doV,
TscL2doV
TdoV2scH,
TdoV2scL
B
Symbol
2
B
Refer to
Example SPI Mode Requirements (Master Mode, CKE = 1)
Characteristic
SCK input high time
(slave mode)
SCK input low time
(slave mode)
Setup time of SDI data input to SCK
edge
Last clock edge of Byte1 to the 1st clock
edge of Byte2
Hold time of SDI data input to SCK edge
SDO data output rise
time
SDO data output fall time
SCK output rise time
(master mode)
SCK output fall time (master mode)
SDO data output valid
after SCK edge
SDO data output setup to SCK edge
Figure 30-1
81
73
MSb IN
MSb
74
71
for load conditions.
75, 76
80
72
BIT6 - - - - - -1
BIT6 - - - -1
Continuous
Single Byte
Continuous
Single Byte
PIC16CXXX
PIC16LCXXX
PIC16CXXX
PIC16LCXXX
PIC16CXXX
PIC16LCXXX
1.25T
1.25T
1.5T
LSb IN
LSb
Min
T
100
100
CY
40
40
—
—
—
—
—
CY
CY
CY
+ 40
+ 30
+ 30
79
78
Typ† Max Units
—
—
—
—
—
—
—
10
20
10
10
20
10
—
—
—
1997 Microchip Technology Inc.
100
25
45
25
25
45
25
50
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1
Note 1
Note 1
Conditions
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