PIC16F819-I/SOTSL Microchip Technology, PIC16F819-I/SOTSL Datasheet - Page 450
![IC PIC MCU FLASH 2KX14 18SOIC](/photos/6/76/67656/150-18-soic_sml.jpg)
PIC16F819-I/SOTSL
Manufacturer Part Number
PIC16F819-I/SOTSL
Description
IC PIC MCU FLASH 2KX14 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F818-ISO.pdf
(176 pages)
4.PIC16F818-ISO.pdf
(6 pages)
5.PIC16F818-ISO.pdf
(8 pages)
6.PIC16F818-ISO.pdf
(8 pages)
Specifications of PIC16F819-I/SOTSL
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
18-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC16F818-ISO PDF datasheet #4
- PIC16F818-ISO PDF datasheet #5
- PIC16F818-ISO PDF datasheet #6
- Current page: 450 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
24.3.1
DS31024A-page 24-8
Slope A/D Timer (ADTMR)
The Slope A/D timer (ADTMR) is comprised of a 16-bit timer (ADTMRH:ADTMRL), which is
incremented every oscillator cycle. The ADTMR registers are cleared by a power-on reset; oth-
erwise the software must initialize it after each conversion. A separate 16-bit capture register
(ADCAPH:ADCAPL) is used to capture the ADTMR count if a Slope A/D capture event occurs
(see below). Both the Slope A/D timer and capture registers are readable and writable. The 16-bit
timer is a read/write register and is cleared on any device reset.
During a conversion one or both of the following events will occur:
• capture event
• timer overflow
In a capture event, the comparator trips when the slope voltage on the CDAC output exceeds the
input voltage from the selected Slope A/D channel, causing the comparator output to transition
from high to low. This causes a transfer of the current timer count to the capture register and sets
the ADCIF flag bit.
An interrupt will be generated if the ADCIE bit is set (interrupt enabled). In addition, GIE and PIE
bits must be set. Software is responsible for clearing the ADCIF flag bit prior to the next conver-
sion cycle. This interrupt can only occur once per conversion cycle.
In a timer overflow condition, the timer rolls over from FFFFh to 0000h, and a capture overflow
flag (OVFIF) is asserted. The timer continues to increment following a timer overflow. An interrupt
can be generated if bit OVFIE is set (interrupt enabled). In addition, the GIE and PIE bits must
be set. Software is responsible for clearing the OVFIF flag bit prior to the next conversion cycle.
Figure 24-2: Example Slope A/D Conversion Cycle
Note 1: Reading or writing the ADTMR register during an Slope A/D conversion cycle can
Note 2: The correct sequence for writing the ADTMR register is HI byte followed by LO byte.
produce unpredictable results and is not recommended.
Reversing this order will prevent the Slope A/D timer from running.
CAPTURE
CLK
ADRST
ADCON0<1>
CDAC
ADCIF
Capture
Register
ADTMR
COUNT
(must be cleared by software)
XX
ADTMR INCREMENTS
XX+1 XX+2 XX+3
XX
XX+8 XX+9
1997 Microchip Technology Inc.
COMPARE
XX+8
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