PIC16F819-I/SOTSL Microchip Technology, PIC16F819-I/SOTSL Datasheet - Page 351
![IC PIC MCU FLASH 2KX14 18SOIC](/photos/6/76/67656/150-18-soic_sml.jpg)
PIC16F819-I/SOTSL
Manufacturer Part Number
PIC16F819-I/SOTSL
Description
IC PIC MCU FLASH 2KX14 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F818-ISO.pdf
(176 pages)
4.PIC16F818-ISO.pdf
(6 pages)
5.PIC16F818-ISO.pdf
(8 pages)
6.PIC16F818-ISO.pdf
(8 pages)
Specifications of PIC16F819-I/SOTSL
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
18-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC16F818-ISO PDF datasheet #4
- PIC16F818-ISO PDF datasheet #5
- PIC16F818-ISO PDF datasheet #6
- Current page: 351 of 688
- Download datasheet (3Mb)
18.5
18.5.1
1997 Microchip Technology Inc.
USART Synchronous Master Transmission
USART Synchronous Master Mode
In Synchronous Master mode, the data is transmitted in a half-duplex manner, i.e. transmission
and reception do not occur at the same time. When transmitting data, the reception is inhibited
and vice versa. Synchronous mode is entered by setting the SYNC bit (TXSTA<4>). In addition,
the SPEN enable bit (RCSTA<7>) is set in order to configure the TX/CK and RX/DT I/O pins to
CK (clock) and DT (data) lines respectively. The Master mode indicates that the processor trans-
mits the master clock on the CK line. The Master mode is entered by setting the CSRC bit
(TXSTA<7>).
The USART transmitter block diagram is shown in
transmit (serial) shift register (TSR). The shift register obtains its data from the read/write transmit
buffer register TXREG. The TXREG register is loaded with data in software. The TSR register is
not loaded until the last bit has been transmitted from the previous load. As soon as the last bit
is transmitted, the TSR is loaded with new data from the TXREG (if available). Once the TXREG
register transfers the data to the TSR register (occurs in one Tcycle), the TXREG is empty and
the TXIF interrupt flag bit is set. The interrupt can be enabled/disabled by setting/clearing enable
the TXIE bit. The TXIF flag bit will be set regardless of the state of the TXIE enable bit and cannot
be cleared in software. It will reset only when new data is loaded into the TXREG register. While
the TXIF flag bit indicates the status of the TXREG register, the TRMT bit (TXSTA<1>) shows the
status of the TSR register. The TRMT bit is a read only bit which is set when the TSR is empty.
No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR
register is empty. The TSR is not mapped in data memory so it is not available to the user.
Transmission is enabled by setting the TXEN bit (TXSTA<5>). The actual transmission will not
occur until the TXREG register has been loaded with data. The first data bit will be shifted out on
the next available rising edge of the clock on the CK line. Data out is stable at the falling edge of
the synchronous clock
TXREG register and then setting the TXEN bit. This is advantageous when slow baud rates are
selected, since the BRG is kept in reset when the TXEN, CREN, and SREN bits are clear. Setting
the TXEN bit will start the BRG, creating a shift clock immediately. Normally when transmission
is first started, the TSR register is empty, so a transfer to the TXREG register will result in an
immediate transfer to TSR resulting in an empty TXREG. Back-to-back transfers are possible.
Clearing the TXEN bit during a transmission will cause the transmission to be aborted and will
reset the transmitter. The DT and CK pins will revert to hi-impedance. If either of the CREN or
SREN bits are set during a transmission, the transmission is aborted and the DT pin reverts to a
hi-impedance state (for a reception). The CK pin will remain an output if the CSRC bit is set (inter-
nal clock). The transmitter logic is not reset although it is disconnected from the pins. In order to
reset the transmitter, the user has to clear the TXEN bit. If the SREN bit is set (to interrupt an
on-going transmission and receive a single word), then after the single word is received, the
SREN bit will be cleared and the serial port will revert back to transmitting since the TXEN bit is
still set. The DT line will immediately switch from hi-impedance receive mode to transmit and start
driving. To avoid this the TXEN bit should be cleared.
In order to select 9-bit transmission, the TX9 bit (TXSTA<6>) should be set and the ninth bit
should be written to the TX9D bit (TXSTA<0>). The ninth bit must be written before writing the
8-bit data to the TXREG register. This is because a data write to the TXREG can result in an
immediate transfer of the data to the TSR register (if the TSR is empty). If the TSR was empty
and the TXREG was written before writing the “new” value to the TX9D bit, the “present” value of
of the TX9D bit is loaded.
(Figure
18-10). The transmission can also be started by first loading the
Section 18. USART
Figure
18-1. The heart of the transmitter is the
DS31018A-page 18-15
18
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