PIC16C717-I/SO Microchip Technology, PIC16C717-I/SO Datasheet - Page 73

• Manufacturer Part Number: PIC16C717-I/SO
• Description: IC MCU OTP 2KX14 A/D PWM 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C717-I/SO

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI
• Number Of I /o: 15
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-SOIC (7.5mm Width)
• Controller Family/series: PIC16C
• No. Of I/o's: 16
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SPI, SSP
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6 bit
• Data Rom Size: 256 B
• Height: 2.31 mm
• Length: 11.53 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4 V
• Width: 7.49 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC16C717I/SO

When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. Buffer
full bit, BF (SSPSTAT<0>), indicates when the SSP-
BUF has been loaded with the received data (transmis-
sion is complete). When the SSPBUF is read, bit BF is
cleared. This data may be irrelevant if the SPI is only a
transmitter. Generally the MSSP Interrupt is used to
determine when the transmission/reception has com-
pleted. The SSPBUF must be read and/or written. If the
interrupt method is not going to be used, then software
polling can be done to ensure that a write collision does
not occur. Example 9-1 shows the loading of the SSP-
BUF (SSPSR) for data transmission.
EXAMPLE 9-1:
The SSPSR is not directly readable or writable, and
can only be accessed by addressing the SSPBUF reg-
ister.
(SSPSTAT) indicates the various status conditions.
FIGURE 9-2:
LOOP BTFSS SSPSTAT, BF
2002 Microchip Technology Inc.
Additionally, the MSSP STATUS register
BSF
GOTO
BCF
MOVF
MOVWF RXDATA
MOVF
MOVWF SSPBUF
STATUS, RP0
LOOP
STATUS, RP0
SSPBUF, W
TXDATA, W
SPI Master SSPM<3:0> = 00xxb
MSb
Loading the SSPBUF
(SSPSR) Register
SPI MASTER/SLAVE CONNECTION
PROCESSOR 1
Serial Input Buffer
Shift Register
(SSPBUF)
(SSPSR)
;Specify Bank 1
;Has data been
;received
;(xmit complete)?
;No
;Specify Bank 0
;Save SSPBUF...
;...in user RAM
;Get next TXDATA
;New data to xmit
LSb
Advance Information
SDO
SCK
SDI
Serial Clock
9.1.2
To enable the serial port, MSSP Enable bit, SSPEN
(SSPCON<5>) must be set. To reset or reconfigure SPI
mode, clear bit SSPEN, re-initialize the SSPCON reg-
isters, and then set bit SSPEN. This configures the
SDI, SDO, SCK and SS pins as serial port pins. For the
pins to behave as the serial port function, some must
have their data direction bits (in the TRIS register)
appropriately programmed. That is:
• SDI is automatically controlled by the SPI module
• SDO must have TRISB<5> cleared
• SCK (Master mode) must have TRISB<2>
• SCK (Slave mode) must have TRISB<2> set
• SS must have TRISB<1> set, and ANSEL<5>
Any serial port function that is not desired may be over-
ridden by programming the corresponding data direc-
tion (TRIS) register to the opposite value.
9.1.3
Figure 9-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge, and latched on the opposite
edge of the clock. Both processors should be pro-
grammed to same Clock Polarity (SSPCON<4>), then
both controllers would send and receive data at the
same time. Whether the data is meaningful (or dummy
data) depends on the application software. This leads
to three scenarios for data transmission:
• Master sends data — Slave sends dummy data
• Master sends data — Slave sends data
• Master sends dummy data — Slave sends data
cleared
cleared
PIC16C717/770/771
SDO
SCK
SDI
ENABLING SPI I/O
TYPICAL CONNECTION
SPI Slave SSPM<3:0> = 010xb
MSb
Serial Input Buffer
Shift Register
PROCESSOR 2
(SSPBUF)
(SSPSR)
LSb
DS41120B-page 71