PIC16LF1936-I/SS Microchip Technology, PIC16LF1936-I/SS Datasheet - Page 365

IC PIC MCU FLASH 512KX14 28-SSOP

PIC16LF1936-I/SS

Manufacturer Part Number
PIC16LF1936-I/SS
Description
IC PIC MCU FLASH 512KX14 28-SSOP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr

Specifications of PIC16LF1936-I/SS

Program Memory Type
FLASH
Program Memory Size
14KB (8K x 14)
Package / Case
28-SSOP
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
25
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
EUSART, MI2C, SPI
Maximum Clock Frequency
32 KHz
Number Of Programmable I/os
35
Number Of Timers
5
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 14 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16LF1936-I/SS
Manufacturer:
MICROCHI
Quantity:
20 000
28.0
Each PIC16 instruction is a 14-bit word containing the
operation code (opcode) and all required operands.
The opcodes are broken into three broad categories.
• Byte Oriented
• Bit Oriented
• Literal and Control
The literal and control category contains the most var-
ied instruction word format.
Table 28-3 lists the instructions recognized by the
MPASM
All instructions are executed within a single instruction
cycle, with the following exceptions, which may take
two or three cycles:
• Subroutine takes two cycles (CALL, CALLW)
• Returns from interrupts or subroutines take two
• Program branching takes two cycles (GOTO, BRA,
• One additional instruction cycle will be used when
One instruction cycle consists of 4 oscillator cycles; for
an oscillator frequency of 4 MHz, this gives a nominal
instruction execution rate of 1 MHz.
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
 2009 Microchip Technology Inc.
cycles (RETURN, RETLW, RETFIE)
BRW, BTFSS, BTFSC, DECFSZ, INCSFZ)
any instruction references an indirect file register
and the file select register is pointing to program
memory.
TM
INSTRUCTION SET SUMMARY
assembler.
Preliminary
28.1
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified,
and the result is stored according to either the instruc-
tion, or the destination designator ‘d’. A read operation
is performed on a register even if the instruction writes
to that register.
TABLE 28-1:
TABLE 28-2:
Field
Field
PIC16F193X/LF193X
mm
DC
PC
TO
PD
W
C
b
d
n
Z
k
x
f
Register file address (0x00 to 0x7F)
Working register (accumulator)
Bit address within an 8-bit file register
Literal field, constant data or label
Don’t care location (= 0 or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
Destination select; d = 0: store result in
d = 1: store result in file register f.
Default is d = 1.
FSR or INDF number. (0-1)
Pre-post increment-decrement mode
selection
Program Counter
Time-out bit
Carry bit
Digit carry bit
Zero bit
Power-down bit
Read-Modify-Write Operations
OPCODE FIELD
DESCRIPTIONS
ABBREVIATION
DESCRIPTIONS
Description
Description
DS41364D-page 365
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