PIC18F25J10-I/SO Microchip Technology, PIC18F25J10-I/SO Datasheet - Page 347

• Manufacturer Part Number: PIC18F25J10-I/SO
• Description: IC PIC MCU FLASH 16KX16 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F25J10-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI/I2C/MSSP/USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Package: 28SOIC W
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILAC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180011 - MODULE PLUG-IN 18F25J10 28SOICAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164331 - MODULE SKT FOR 28SSOP 18F45J10
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced PWM Mode. See PWM (ECCP Module).......... 133
Enhanced Universal Synchronous Asynchronous
Equations
Errata .................................................................................... 6
EUSART
Extended Instruction Set
External Clock Input (EC Modes)........................................ 24
F
Fail-Safe Clock Monitor............................................. 229, 238
Fast Register Stack............................................................. 50
Firmware Instructions........................................................ 241
Flash Configuration Words ............................................... 229
Flash Program Memory ...................................................... 67
© 2007 Microchip Technology Inc.
Receiver Transmitter (EUSART). See EUSART.
A/D Acquisition Time................................................. 214
A/D Minimum Charging Time.................................... 214
Asynchronous Mode ................................................. 197
Baud Rate Generator
Baud Rate Generator (BRG)..................................... 191
Synchronous Master Mode ....................................... 203
Synchronous Slave Mode ......................................... 206
ADDFSR ................................................................... 284
ADDULNK................................................................. 284
and Using MPLAB Tools........................................... 290
CALLW...................................................................... 285
Considerations for Use ............................................. 288
MOVSF ..................................................................... 285
MOVSS ..................................................................... 286
PUSHL ...................................................................... 286
SUBFSR ................................................................... 287
SUBULNK ................................................................. 287
Syntax ....................................................................... 283
Interrupts in Power-Managed Modes........................ 239
POR or Wake-up from Sleep .................................... 239
WDT During Oscillator Failure .................................. 238
Associated Registers .................................................. 75
Control Registers ........................................................ 68
Erase Sequence ......................................................... 72
Erasing........................................................................ 72
Operation During Code-Protect .................................. 75
12-Bit Break Transmit and Receive .................. 202
Associated Registers, Receive ......................... 200
Associated Registers, Transmit ........................ 198
Auto-Wake-up on Sync Break .......................... 200
Receiver............................................................ 199
Setting Up 9-Bit Mode with Address Detect...... 199
Transmitter........................................................ 197
Operation in Power-Managed Mode ................. 191
Associated Registers ........................................ 192
Auto-Baud Rate Detect ..................................... 195
Baud Rate Error, Calculating ............................ 192
Baud Rates, Asynchronous Modes .................. 193
High Baud Rate Select (BRGH Bit) .................. 191
Sampling ........................................................... 191
Associated Registers, Receive ......................... 205
Associated Registers, Transmit ........................ 204
Reception.......................................................... 205
Transmission .................................................... 203
Associated Registers, Receive ......................... 207
Associated Registers, Transmit ........................ 206
Reception.......................................................... 207
Transmission .................................................... 206
EECON1 and EECON2 ...................................... 68
TABLAT (Table Latch) ........................................ 70
TBLPTR (Table Pointer) ..................................... 70
Preliminary
PIC18F45J10 FAMILY
FSCM. See Fail-Safe Clock Monitor.
G
GOTO ............................................................................... 262
H
Hardware Multiplier............................................................. 77
I
I/O Ports ............................................................................. 93
I
INCF ................................................................................. 262
INCFSZ............................................................................. 263
In-Circuit Debugger........................................................... 240
In-Circuit Serial Programming (ICSP)....................... 229, 240
Indexed Literal Offset Addressing
2
C Mode (MSSP)
Reading ...................................................................... 71
Table Pointer
Table Pointer Boundaries ........................................... 70
Table Reads and Table Writes ................................... 67
Write Sequence .......................................................... 73
Writing To ................................................................... 73
Introduction................................................................. 77
Operation.................................................................... 77
Performance Comparison........................................... 77
Acknowledge Sequence Timing ............................... 179
Associated Registers................................................ 185
Baud Rate Generator ............................................... 172
Bus Collision
Clock Arbitration ....................................................... 173
Clock Stretching ....................................................... 165
Clock Synchronization and the CKP Bit ................... 166
Effects of a Reset ..................................................... 180
General Call Address Support .................................. 169
I
Master Mode............................................................. 170
Multi-Master Communication, Bus Collision and
Multi-Master Mode.................................................... 180
Operation.................................................................. 159
Read/Write Bit Information (R/W Bit)................ 159, 160
Registers .................................................................. 155
Serial Clock (SCKx/SCLx) ........................................ 160
Slave Mode............................................................... 159
Sleep Operation........................................................ 180
Stop Condition Timing .............................................. 179
and Standard PIC18 Instructions.............................. 288
2
C Clock Rate w/BRG ............................................. 172
Boundaries Based on Operation ........................ 70
Protection Against Spurious Writes .................... 75
Unexpected Termination .................................... 75
Write Verify ......................................................... 75
During a Repeated Start Condition................... 183
During a Stop Condition ................................... 184
10-Bit Slave Receive Mode (SEN = 1) ............. 165
10-Bit Slave Transmit Mode ............................. 165
7-Bit Slave Receive Mode (SEN = 1) ............... 165
7-Bit Slave Transmit Mode ............................... 165
Baud Rate Generator ....................................... 172
Operation.......................................................... 171
Reception ......................................................... 176
Repeated Start Condition Timing ..................... 175
Start Condition Timing ...................................... 174
Transmission .................................................... 176
Arbitration ......................................................... 180
Addressing ....................................................... 159
Reception ......................................................... 160
Transmission .................................................... 160
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