PIC16LC621A-04I/P Microchip Technology, PIC16LC621A-04I/P Datasheet - Page 61

• Manufacturer Part Number: PIC16LC621A-04I/P
• Description: IC MCU OTP 1KX14 COMP 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC621A-04I/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 13
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: OTP
• Ram Size: 96 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• Processor Series: PIC16LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 96 B
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 8
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

9.8
The Power-down mode is entered by executing a
SLEEP
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit in the STATUS register is
cleared, the TO bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before
impedance).
For lowest current consumption in this mode, all I/O
pins should be either at V
circuitry drawing current from the I/O pin and the
comparators and V
are hi-impedance inputs should be pulled high or low
externally to avoid switching currents caused by float-
ing inputs. The T0CKI input should also be at V
V
from on chip pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (V
9.8.1
The device can wake-up from SLEEP through one of
the following events:
1.
2.
3.
FIGURE 9-18:
 2003 Microchip Technology Inc.
(INTCON<1>)
(INTCON<7>)
INTF flag
Note 1: XT, HS or LP Oscillator mode assumed.
GIE bit
SS
INSTRUCTION FLOW
Note:
CLKOUT(4)
Instruction
fetched
Instruction
executed
External RESET input on MCLR pin
Watchdog Timer Wake-up (if WDT was enabled)
Interrupt from RB0/INT pin, RB Port change, or
the Peripheral Interrupt (Comparator).
for lowest current consumption. The contribution
INT pin
OSC1
SLEEP
2: T
3: GIE = '1' assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = '0',
4: CLKOUT is not available in these Osc modes, but shown here for timing reference.
PC
instruction.
Power-Down Mode (SLEEP)
execution will continue in-line.
It should be noted that a RESET generated
by a WDT time-out does not drive MCLR
pin low.
WAKE-UP FROM SLEEP
OST
Inst(PC) = SLEEP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
was executed (driving high, low, or hi-
Inst(PC - 1)
= 1024T
PC
REF
WAKE-UP FROM SLEEP THROUGH INTERRUPT
should be disabled. I/O pins that
OSC
DD
(drawing not to scale) This delay will not be there for RC Osc mode.
Inst(PC + 1)
SLEEP
or V
PC+1
SS
with no external
Processor in
SLEEP
IHMC
PC+2
DD
).
Tost(2)
or
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Interrupt Latency
Inst(PC + 2)
Inst(PC + 1)
(Note 2)
The first event will cause a device RESET. The two
latter events are considered a continuation of program
execution. The TO and PD bits in the STATUS register
can be used to determine the cause of device RESET.
PD bit, which is set on power-up, is cleared when
SLEEP is invoked. TO bit is cleared if WDT wake-up
occurred.
When the
next instruction (PC + 1) is pre-fetched. For the device
to wake-up through an interrupt event, the correspond-
ing interrupt enable bit must be set (enabled). Wake-up
is regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the
set (enabled), the device executes the instruction after
the
rupt address (0004h). In cases where the execution of
the instruction following
user should have an
The WDT is cleared when the device wakes up from
SLEEP, regardless of the source of wake-up.
PC+2
Note:
SLEEP
Dummy cycle
SLEEP
If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the correspond-
ing interrupt flag bits set, the device will
immediately wake-up from SLEEP. The
SLEEP instruction is completely executed.
instruction and then branches to the inter-
PC + 2
instruction is being executed, the
SLEEP
NOP
SLEEP
PIC16C62X
Inst(0004h)
Dummy cycle
after the
0004h
instruction. If the GIE bit is
is not desirable, the
SLEEP
DS30235J-page 59
Inst(0005h)
Inst(0004h)
0005h
instruction.