PIC16LC621A-04I/P Microchip Technology, PIC16LC621A-04I/P Datasheet - Page 51

• Manufacturer Part Number: PIC16LC621A-04I/P
• Description: IC MCU OTP 1KX14 COMP 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC621A-04I/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 13
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: OTP
• Ram Size: 96 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• Processor Series: PIC16LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 96 B
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 8
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

9.3
The PIC16C62X differentiates between various kinds
of RESET:
a)
b)
c)
d)
e)
f)
Some registers are not affected in any RESET
condition Their status is unknown on POR and
unchanged in any other RESET. Most other registers
are reset to a “RESET state” on Power-on Reset,
FIGURE 9-6:
 2003 Microchip Technology Inc.
V
MCLR/
OSC1/
CLKIN
PP
V
Pin
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during SLEEP
WDT Reset (normal operation)
WDT wake-up (SLEEP)
Brown-out Reset (BOR)
DD
Pin
RESET
On-chip
RC OSC
OST/PWRT
Brown-out
V
Module
(1)
detect
WDT
DD
Reset
rise
OST
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
PWRT
10-bit Ripple-counter
Reset
10-bit Ripple-counter
WDT
Time-out
BODEN
Power-on Reset
External
RESET
SLEEP
Enable PWRT
Enable OST
MCLR Reset, WDT Reset and MCLR Reset during
SLEEP. They are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. TO and PD bits are set or cleared differently
in different RESET situations as indicated in Table 9-2.
These bits are used in software to determine the nature
of the RESET. See Table 9-5 for a full description of
RESET states of all registers.
A simplified block diagram of the on-chip RESET circuit
is shown in Figure 9-6.
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Table 12-5 for pulse width
specification.
See Table 9-1 for time-out situations.
PIC16C62X
S
R
DS30235J-page 49
Q
Q
Chip_Reset