PIC16C716-04/SS Microchip Technology, PIC16C716-04/SS Datasheet - Page 12
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PIC16C716-04/SS
Manufacturer Part Number
PIC16C716-04/SS
Description
IC MCU OTP 2KX14 A/D PWM 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16C716-04P.pdf
(106 pages)
2.PIC16C716-04P.pdf
(14 pages)
3.PIC16C712-04P.pdf
(109 pages)
Specifications of PIC16C716-04/SS
Core Size
8-Bit
Program Memory Size
3.5KB (2K x 14)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
4MHz
Number Of I /o
13
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
20-SSOP
Controller Family/series
PIC16C
No. Of I/o's
13
Ram Memory Size
128Byte
Cpu Speed
4MHz
No. Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
309-1016 - ADAPTER 20-SSOP TO 18-DIP
Eeprom Size
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
PIC16C712/716
TABLE 2-1
DS41106A-page 12
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ’0’,
Note 1: These registers can be addressed from either bank.
80h
81h
82h
83h
84h
85h
86h
87h
88h-89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh-91h
92h
93h-9Eh
9Fh
Addr
Bank 1
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents
3: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved. Always maintain these bits clear.
5: On any device reset, these pins are configured as inputs.
6: This is the value that will be in the port output latch.
7: Reserved bits; Do Not Use.
Name
Shaded locations are unimplemented, read as ’0’.
are transferred to the upper byte of the program counter.
INDF
OPTION_
REG
PCL
STATUS
FSR
TRISA
TRISB
TRISCCP
PCLATH
INTCON
PIE1
PCON
PR2
ADCON1
(1)
(1)
—
—
—
—
(1)
(1)
(1,2)
(1)
SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter’s (PC) Least Significant Byte
Indirect data memory address pointer
PORTB Data Direction Register
Unimplemented
Unimplemented
Unimplemented
Timer2 Period Register
Unimplemented
RBPU
IRP
Bit 7
—
GIE
—
—
—
—
—
(7)
(4)
INTEDG
RP1
PEIE
ADIE
Bit 6
—
—
—
—
—
(7)
(4)
T0CS
Bit 5
T0IE
RP0
—
—
—
—
—
—
(7)
(7)
PORTA Data Direction Register
Write Buffer for the upper 5 bits of the Program Counter
Preliminary
T0SE
Bit 4
INTE
—
TO
—
—
—
(7)
RBIE
Bit 3
PSA
—
PD
—
—
—
(7)
CCP1IE
PCFG2
TCCP
Bit 2
T0IF
PS2
—
Z
TMR2IE
PCFG1
Bit 1
INTF
POR
—
PS1
DC
(7)
1999 Microchip Technology Inc.
TMR1IE
PCFG0
TT1CK
RBIF
Bit 0
BOR
PS0
C
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
rr01 1xxx rr0q quuu
xxxx xxxx uuuu uuuu
--x1 1111 --x1 1111
1111 1111 1111 1111
xxxx x1x1 xxxx x1x1
---0 0000 ---0 0000
0000 000x 0000 000u
-0-- -000 -0-- -000
---- --qq ---- --uu
1111 1111 1111 1111
---- -000
Value on:
POR,
BOR
—
—
—
—
other resets
Value on all
---- -000
(4)
—
—
—
—