PIC16F818T-E/SO Microchip Technology, PIC16F818T-E/SO Datasheet - Page 333

• Manufacturer Part Number: PIC16F818T-E/SO
• Description: IC PIC MCU FLASH 1KX14 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F818T-E/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 18-SOIC (7.5mm Width)
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: I2C, SPI, SSP
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.6
17.6.1
1997 Microchip Technology Inc.
Master SSP Module / Basic SSP Module Compatibility
Initialization
Example 17-2:
When changing from the SPI in the Basic SSP module, the SSPSTAT register contains two addi-
tional control bits. These bits are:
• SMP, SPI data input sample phase
• CKE, SPI Clock Edge Select
To be compatible with the SPI of the Master SSP module, these bits must be appropriately con-
figured. If these bits are not at the states shown in
occur.
Table 17-4: New bit States for Compatibility
Basic SSP Module
CLRF
CLRF
BSF
MOVLW
MOVWF
BSF
BSF
BCF
BSF
MOVLW
MOVWF
CKP
1
0
STATUS
SSPSTAT
SSPSTAT, CKE ; CKE = 1
0x31
SSPCON
STATUS, RP0
PIE, SSPIE
STATUS, RP0
INTCON, GIE
DataByte
SSPBUF
SPI Master Mode Initialization
Preliminary
CKP
; Bank 0
; SMP = 0, CKE = 0, and clear status bits
; Set up SPI port, Master mode, CLK/16,
;
;
; Bank 1
; Enable SSP interrupt
; Bank 0
; Enable, enabled interrupts
; Data to be Transmitted
;
; Start Transmission
1
0
Data xmit on falling edge (CKE=1 & CKP=1)
Data sampled in middle (SMP=0 & Master mode)
Could move data from RAM location
Master SSP Module
CKE
0
0
Section 17. MSSP
Table
17-4, improper SPI communication may
SMP
0
0
DS31017A-page 17-57
17