AT89S52-24JU Atmel, AT89S52-24JU Datasheet - Page 17
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AT89S52-24JU
Manufacturer Part Number
AT89S52-24JU
Description
IC MCU 8K FLASH 24MHZ 44-PLCC
Manufacturer
Atmel
Series
89Sr
Datasheet
1.AT89S52-24AU.pdf
(38 pages)
Specifications of AT89S52-24JU
Core Processor
8051
Core Size
8-Bit
Speed
24MHz
Connectivity
UART/USART
Peripherals
WDT
Number Of I /o
32
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Package
44PLCC
Device Core
8051
Family Name
89S
Maximum Speed
24 MHz
Operating Supply Voltage
5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
32
Interface Type
UART
Number Of Timers
3
Processor Series
AT89x
Core
8051
Data Ram Size
256 B
Maximum Clock Frequency
33 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
AT89ISP
Minimum Operating Temperature
- 40 C
Eeprom Memory
0 Bytes
Input Output
32
Interface
UART
Memory Type
Flash
Number Of Bits
8
Package Type
44-pin PLCC
Programmable Memory
8K Bytes
Timers
3-16-bit
Voltage, Range
4-5.5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Figure 12-1. Timer 2 in Clock-Out Mode
13. Interrupts
1919D–MICRO–6/08
(T2EX)
P1.0
P1.1
(T2)
The AT89S52 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three
timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown
in
Each of these interrupt sources can be individually enabled or disabled by setting or clearing a
bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all
interrupts at once.
Note that
write a 1 to this bit position, since it may be used in future AT89 products.
Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Nei-
ther of these flags is cleared by hardware when the service routine is vectored to. In fact, the
service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt,
and that bit will have to be cleared in software.
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers
overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag,
TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.
Figure
OSC
TRANSITION
DETECTOR
13-1.
Table 13-1
÷2
EXEN2
shows that bit position IE.6 is unimplemented. User software should not
C/T2 BIT
EXF2
TR2
÷2
TIMER 2
INTERRUPT
(8-BITS)
RCAP2L RCAP2H
TL2
T2OE (T2MOD.1)
(8-BITS)
TH2
AT89S52
17