PIC12LC671-04I/P Microchip Technology, PIC12LC671-04I/P Datasheet - Page 11
![IC MCU OTP 1KX14 LV A/D 8DIP](/photos/16/0/160065/8-pdip-angled-300dpi-lyrd_sml.jpg)
PIC12LC671-04I/P
Manufacturer Part Number
PIC12LC671-04I/P
Description
IC MCU OTP 1KX14 LV A/D 8DIP
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Specifications of PIC12LC671-04I/P
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DIP (0.300", 7.62mm)
Processor Series
PIC12LC
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
5
Number Of Timers
8
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
- 40 C
On-chip Adc
8
For Use With
309-1051 - ADAPTER 8-DIP BD W/2 SO PLUGS
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
4.0
4.1
The PIC12C67X has a 13-bit program counter capable
of addressing an 8K x 14 program memory space.
For the PIC12C671 and the PIC12CE673, the first 1K x
14 (0000h-03FFh) is implemented.
For the PIC12C672 and the PIC12CE674, the first 2K
x 14 (0000h-07FFh) is implemented. Accessing a loca-
tion above the physically implemented address will
cause a wraparound. The reset vector is at 0000h and
the interrupt vector is at 0004h.
FIGURE 4-1:
1999 Microchip Technology Inc.
CALL, RETURN
RETFIE, RETLW
MEMORY ORGANIZATION
Program Memory Organization
Peripheral
PIC12CE674 only)
On-Chip Program
(PIC12C672 and
PIC12C67X PROGRAM
MEMORY MAP AND STACK
Stack Level 1
Stack Level 8
Reset Vector
Memory
PC<12:0>
Interrupt Vector
13
03FFh
0400h
0000h
0004h
0005h
07FFh
0800h
1FFFh
4.2
The data memory is partitioned into two banks, which
contain the General Purpose Registers and the Special
Function Registers. Bit RP0 is the bank select bit.
RP0 (STATUS<5>) = 1
RP0 (STATUS<5>) = 0
Each Bank extends up to 7Fh (128 bytes). The lower
locations of each Bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers implemented as
static RAM. Both Bank 0 and Bank 1 contain Special
Function Registers. Some "high use" Special Function
Registers from Bank 0 are mirrored in Bank 1 for code
reduction and quicker access.
Also note that F0h through FFh on the PIC12C67X is
mapped into Bank 0 registers 70h-7Fh as common
RAM.
4.2.1
The register file can be accessed either directly or indi-
rectly
(Section 4.5).
through
Data Memory Organization
GENERAL PURPOSE REGISTER FILE
the
File
PIC12C67X
Bank 1
Bank 0
Select
DS30561B-page 11
Register
FSR