PIC16C770/P Microchip Technology, PIC16C770/P Datasheet - Page 36

• Manufacturer Part Number: PIC16C770/P
• Description: IC MCU CMOS A/D 2K 20MHZ 20-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C770/P

• Program Memory Type: OTP
• Program Memory Size: 3.5KB (2K x 14)
• Package / Case: 20-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 15
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C/SPI/SSP
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• On-chip Adc: 6-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA16XP200 - ADAPTER ICE 20DIP/SOIC/SSOPAC164028 - MODULE SKT PROMATEII 20SOIC/DIP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16C717/770/771
REGISTER 3-2:
REGISTER 3-3:
DS41120B-page 34
bit 7-0
bit 7-0
WEAK PULL-UP PORTB REGISTER (WPUB: 95h)
INTERRUPT-ON-CHANGE PORTB REGISTER (IOCB: 96h)
bit 7
WPUB<7:0>: PORTB Weak Pull-Up Control bits
1 = Weak pull-up enabled
0 = Weak pull-up disabled
Legend:
R = Readable bit
- n = Value at POR
bit 7
IOCB<7:0>: Interrupt-on-Change PORTB Control bits
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
Legend:
R = Readable bit
- n = Value at POR
WPUB7
Note:
IOCB7
R/W-1
R/W-1
Note 1: For the WPUB register setting to take effect, the RBPU bit in the OPTION_REG
2: The weak pull-up device is automatically disabled if the pin is in Output mode
The interrupt enable bits GIE and RBIE in the INTCON Register must be set for indi-
vidual interrupts to be recognized.
register must be cleared.
(TRIS = 0).
WPUB6
IOCB6
R/W-1
R/W-1
WPUB5
IOCB5
R/W-1
R/W-1
W = Writable bit
’1’ = Bit is set
W = Writable bit
’1’ = Bit is set
WPUB4
IOCB4
R/W-1
R/W-1
WPUB3
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
IOCB3
R/W-1
R/W-0
WPUB2
IOCB2
R/W-1
R/W-0
2002 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
WPUB1
IOCB1
R/W-1
R/W-0
WPUB0
IOCB0
R/W-1
R/W-0
bit 0
bit 0