ATTINY25V-10SSU Atmel, ATTINY25V-10SSU Datasheet - Page 150
![MCU AVR 2K ISP FLASH 1.8V 8-SOIC](/photos/6/50/65032/453-8-soic_sml.jpg)
ATTINY25V-10SSU
Manufacturer Part Number
ATTINY25V-10SSU
Description
MCU AVR 2K ISP FLASH 1.8V 8-SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY25V-10SSU
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Processor Series
ATTINY2x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
USI
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
4-ch x 10-bit
Package
8SOIC
Device Core
AVR
Family Name
ATtiny
Maximum Speed
10 MHz
Operating Supply Voltage
2.5|3.3|5 V
For Use With
ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIPATAVRBC100 - REF DESIGN KIT BATTERY CHARGER770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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• Bit 4 – CTPB: Clear Temporary Page Buffer
If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be
cleared and the data will be lost.
• Bit 3 – RFLB: Read Fuse and Lock Bits
An LPM instruction within three cycles after RFLB and SPMEN are set in the SPMCSR Register,
will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destina-
tion register. See
“EEPROM Write Prevents Writing to SPMCSR” on page 147
for details.
• Bit 2 – PGWRT: Page Write
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock
cycles executes Page Write, with the data stored in the temporary buffer. The page address is
taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit
will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four
clock cycles. The CPU is halted during the entire Page Write operation.
• Bit 1 – PGERS: Page Erase
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock
cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The
data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase,
or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire
Page Write operation.
• Bit 0 – SPMEN: Store Program Memory Enable
This bit enables the SPM instruction for the next four clock cycles. If set to one together with
RSIG, CTPB, RFLB, PGWRT or PGERS, the following LPM/SPM instruction will have a special
meaning, as described elsewhere.
If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the tem-
porary page buffer addressed by the Z-pointer. The LSB of the Z-pointer is ignored. The SPMEN
bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed
within four clock cycles. During Page Erase and Page Write, the SPMEN bit remains high until
the operation is completed.
ATtiny25/45/85
150
2586M–AVR–07/10
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