ATTINY25V-10SSU Atmel, ATTINY25V-10SSU Datasheet - Page 131
![MCU AVR 2K ISP FLASH 1.8V 8-SOIC](/photos/6/50/65032/453-8-soic_sml.jpg)
ATTINY25V-10SSU
Manufacturer Part Number
ATTINY25V-10SSU
Description
MCU AVR 2K ISP FLASH 1.8V 8-SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY25V-10SSU
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Processor Series
ATTINY2x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
USI
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
4-ch x 10-bit
Package
8SOIC
Device Core
AVR
Family Name
ATtiny
Maximum Speed
10 MHz
Operating Supply Voltage
2.5|3.3|5 V
For Use With
ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIPATAVRBC100 - REF DESIGN KIT BATTERY CHARGER770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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2586M–AVR–07/10
Figure 17-6. ADC Timing Diagram, Auto Triggered Conversion
In Free Running mode, a new conversion will be started immediately after the conversion com-
pletes, while ADSC remains high.
Figure 17-7. ADC Timing Diagram, Free Running Conversion
For a summary of conversion times, see
Table 17-1.
Cycle Number
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
ADCL
Condition
First conversion
Normal conversions
Auto Triggered conversions
Prescaler
Reset
ADC Conversion Time
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
MUX and REFS
Update
1
Conversion
2
Complete
One Conversion
3
(Cycles from Start of Conversion)
11
Sample &
Hold
4
12
5
Sample & Hold
Table
13
6
13.5
1.5
2
17-1.
7
One Conversion
Next Conversion
1
Sign and MSB of Result
LSB of Result
8
2
MUX and REFS
Update
9
10
Conversion
3
Complete
11
Sample & Hold
4
Total Conversion Time
12
13
(Cycles)
13.5
25
13
Sign and MSB of Result
LSB of Result
Next Conversion
1
Prescaler
Reset
2
131
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