AT90PWM1-16SU Atmel, AT90PWM1-16SU Datasheet - Page 164

• Manufacturer Part Number: AT90PWM1-16SU
• Description: MCU AVR 8K FLASH 16MHZ 24-SOIC
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM1-16SU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 24-SOIC (7.5mm Width)
• Processor Series: AT90PWMx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 2
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRFBKIT, ATAVRISP2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.26.2
16.26.3
16.26.4
16.26.5
164
AT90PWM1
PSC0 Interrupt Mask Register – PIM0
PSC2 Interrupt Mask Register – PIM2
PSC0 Interrupt Flag Register – PIFR0
PSC2 Interrupt Flag Register – PIFR2
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
• Bit 5 – PSEIEn : PSC n Synchro Error Interrupt Enable
When this bit is set, the PSEIn bit (if set) generate an interrupt.
• Bit 4 – PEVEnB : PSC n External Event B Interrupt Enable
When this bit is set, an external event which can generates a capture from Retrigger/Fault block
B generates also an interrupt.
• Bit 3 – PEVEnA : PSC n External Event A Interrupt Enable
When this bit is set, an external event which can generates a capture from Retrigger/Fault block
A generates also an interrupt.
• Bit 0 – PEOPEn : PSC n End Of Cycle Interrupt Enable
When this bit is set, an interrupt is generated when PSC reaches the end of the whole cycle.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
• Bit 7 – POACnB : PSC n Output B Activity (not implemented on AT90PWM1)
This bit is set by hardware each time the output PSCOUTn1 changes from 0 to 1 or from 1 to 0.
Must be cleared by software by writing a one to its location.
This feature is useful to detect that a PSC output doesn’t change due to a freezen external input
signal.
• Bit 6 – POACnA : PSC n Output A Activity (not implemented on AT90PWM1)
This bit is set by hardware each time the output PSCOUTn0 changes from 0 to 1 or from 1 to 0.
Must be cleared by software by writing a one to its location.
POAC0B
POAC2B
7
R
0
7
R
0
7
R
0
7
R
0
-
-
POAC0A
POAC2A
R
R
R
R
6
0
6
0
6
0
6
0
-
-
PSEIE0
PSEIE2
PSEI0
PSEI2
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
PEVE0B
PEVE2B
PEV0B
PEV2B
R/W
R/W
R/W
R/W
4
0
4
0
4
0
4
0
PEVE0A
PEVE2A
PEV0A
PEV2A
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
PRN01
PRN21
R
R
R
R
2
0
2
0
2
0
2
0
-
-
PRN00
PRN20
R
R
R
R
1
0
1
0
1
0
1
0
-
-
PEOPE0
PEOPE2
PEOP2
PEOP2
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
4378C–AVR–09/08
PIFR0
PIFR2
PIM0
PIM2