PIC16F1936-E/SP Microchip Technology, PIC16F1936-E/SP Datasheet - Page 334
![IC PIC MCU FLASH 512KX14 28SPDIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC16F1936-E/SP
Manufacturer Part Number
PIC16F1936-E/SP
Description
IC PIC MCU FLASH 512KX14 28SPDIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC16LF1933-ISS.pdf
(508 pages)
3.PIC16LF1933-ISS.pdf
(46 pages)
4.PIC16F1936-ISS.pdf
(2 pages)
5.PIC16F1936-ISS.pdf
(10 pages)
6.PIC16F1936-ISS.pdf
(40 pages)
7.PIC16F1936-ISS.pdf
(30 pages)
8.PIC16F1936-ISS.pdf
(12 pages)
9.PIC16LF1934-IML.pdf
(418 pages)
Specifications of PIC16F1936-E/SP
Program Memory Type
FLASH
Program Memory Size
14KB (8K x 14)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
25
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
EUSART/MI2C/SPI
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
25
Number Of Timers
5
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
11-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PIC16F722-ISS PDF datasheet
- PIC16LF1933-ISS PDF datasheet #2
- PIC16LF1933-ISS PDF datasheet #3
- PIC16F1936-ISS PDF datasheet #4
- PIC16F1936-ISS PDF datasheet #5
- PIC16F1936-ISS PDF datasheet #6
- PIC16F1936-ISS PDF datasheet #7
- PIC16F1936-ISS PDF datasheet #8
- PIC16LF1934-IML PDF datasheet #9
- Current page: 334 of 418
- Download datasheet (7Mb)
PIC16F193X/LF193X
23.5
Depending on the application, good programming
practice may dictate that the value written to the data
EEPROM or program memory should be verified (see
Example 23-6) to the desired value to be written.
EXAMPLE 23-6:
23.5.1
The data EEPROM is a high-endurance, byte
addressable array that has been optimized for the
storage of frequently changing information (e.g.,
program variables or other data that are updated often).
When variables in one section change frequently, while
variables in another section do not change, it is possible
to exceed the total number of write cycles to the
EEPROM (specification D124) without exceeding the
total number of write cycles to a single byte
(specifications D120 and D120A). If this is the case,
then a refresh of the array must be performed. For this
reason, variables that change infrequently (such as
constants, IDs, calibration, etc.) should be stored in
Flash program memory.
TABLE 23-2:
DS41364A-page 332
EECON1
EECON2 EEPROM Control Register 2 (not a physical register)
EEADRL EEADRL7 EEADRL6 EEADRL5 EEADRL4 EEADRL3 EEADRL2 EEADRL1 EEADRL0
EEADRH
EEDATL
EEDATH
INTCON
PIE2
PIR2
Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends upon condition.
BANKSEL EEDATL
MOVF
BSF
XORWF
BTFSS
GOTO
:
Name
*
Write Verify
EEDATL, W
EECON1, RD ;YES, Read the
EEDATL, W
STATUS, Z
WRITE_ERR
Shaded cells are not used by data EEPROM module.
Page provides register information.
USING THE DATA EEPROM
EEDATL7 EEDATL6 EEDATL5 EEDATL4 EEDATL3 EEDATL2 EEDALT1 EEDATL0
EEPGD
OSFIE
OSFIF
Bit 7
GIE
—
—
SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM
WRITE VERIFY
EEADRH6 EEADRH5 EEADRH4 EEADRH3 EEADRH2 EEADRH1 EEADRH0
;
;EEDATL not changed
;from previous write
;value written
;
;Is data the same
;No, handle error
;Yes, continue
CFGS
PEIE
C2IE
Bit 6
C2IF
—
EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0
TMR0IE
LWLO
Bit 5
C1IE
C1IF
FREE
Bit 4
INTE
EEIE
EEIF
Preliminary
WRERR
BCLIE
IOCIE
BCLIF
Bit 3
23.6
There are conditions when the user may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, WREN is cleared. Also, the
Power-up
EEPROM write.
The write initiate sequence and the WREN bit together
help prevent an accidental write during:
• Brown-out
• Power Glitch
• Software Malfunction
23.7
Data memory can be code-protected by programming
the CPD bit in the Configuration Word Register 1
(Register 10-1) to ‘0’.
When the data memory is code-protected, only the
CPU is able to read and write data to the data
EEPROM. It is recommended to code-protect the
program memory when code-protecting data memory.
This prevents anyone from replacing your program with
a program that will access the contents of the data
EEPROM.
TMR0IF
WREN
LCDIE
Protection Against Spurious Write
Data EEPROM Operation During
Code-Protect
LCDIF
Bit 2
Timer
Bit 1
INTF
WR
(64 ms
—
—
© 2008 Microchip Technology Inc.
CCP2IE
CCP2IF
IOCIF
duration)
Bit 0
RD
Register
on Page
324*
prevents
323
322
322
322
322
73
75
78
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