PIC16C712-04/P Microchip Technology, PIC16C712-04/P Datasheet - Page 17
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PIC16C712-04/P
Manufacturer Part Number
PIC16C712-04/P
Description
IC MCU OTP 1KX14 A/D PWM 18DIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16C716-04P.pdf
(106 pages)
2.PIC16C716-04P.pdf
(14 pages)
3.PIC16C712-04P.pdf
(109 pages)
Specifications of PIC16C712-04/P
Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
4MHz
Number Of I /o
13
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
18-DIP (0.300", 7.62mm)
Controller Family/series
PIC16C
No. Of I/o's
13
Ram Memory Size
128Byte
Cpu Speed
4MHz
No. Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16C712-04/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
2.2.2.5
This register contains the individual flag bits for the
peripheral interrupts.
FIGURE 2-8:
bit7
1999 Microchip Technology Inc.
bit 7:
bit 6:
bit 5-3: Unimplemented: Read as ‘0’
bit 2:
bit 1:
bit 0:
U-0
—
PIR1 REGISTER
Unimplemented: Read as ‘0’
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
R/W-0
ADIF
PIR1 REGISTER (ADDRESS 0Ch)
U-0
—
U-0
—
R/W-0
—
Preliminary
CCP1IF
R/W-0
TMR2IF
R/W-0
Note:
TMR1IF
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
R/W-0
PIC16C712/716
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
- n = Value at POR reset
read as ‘0’
DS41106A-page 17