PIC16F722-I/SO Microchip Technology, PIC16F722-I/SO Datasheet - Page 44
![IC PIC MCU FLASH 2KX14 28-SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC16F722-I/SO
Manufacturer Part Number
PIC16F722-I/SO
Description
IC PIC MCU FLASH 2KX14 28-SOIC
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.AC164112.pdf
(302 pages)
2.PIC16F722-ISS.pdf
(8 pages)
3.PIC16F722-ISS.pdf
(10 pages)
4.PIC16F722-ISS.pdf
(32 pages)
5.PIC16F722-ISS.pdf
(2 pages)
6.PIC16F722-ISS.pdf
(8 pages)
7.PIC16LF724-EP.pdf
(266 pages)
Specifications of PIC16F722-I/SO
Program Memory Type
FLASH
Program Memory Size
3.5KB (2K x 14)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
I2C/SCI/SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
25
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120
Minimum Operating Temperature
- 40 C
On-chip Adc
11-ch x 8-bit
Controller Family/series
PIC16F
No. Of I/o's
25
Ram Memory Size
128Byte
Cpu Speed
20MHz
No. Of Timers
3
Embedded Interface Type
I2C, SPI, USART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPICE2000 - EMULATOR MPLAB-ICE 2000 POD
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F722-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- AC164112 PDF datasheet
- PIC16F722-ISS PDF datasheet #2
- PIC16F722-ISS PDF datasheet #3
- PIC16F722-ISS PDF datasheet #4
- PIC16F722-ISS PDF datasheet #5
- PIC16F722-ISS PDF datasheet #6
- PIC16LF724-EP PDF datasheet #7
- Current page: 44 of 302
- Download datasheet (5Mb)
PIC16F72X/PIC16LF72X
4.1
Interrupts are disabled upon any device Reset. They
are enabled by setting the following bits:
• GIE bit of the INTCON register
• Interrupt Enable bit(s) for the specific interrupt
• PEIE bit of the INTCON register (if the Interrupt
The INTCON, PIR1 and PIR2 registers record individ-
ual interrupts via Interrupt Flag bits. Interrupt Flag bits
will be set, regardless of the status of the GIE, PEIE
and individual Interrupt Enable bits.
The following events happen when an interrupt event
occurs while the GIE bit is set:
• Current prefetched instruction is flushed
• GIE bit is cleared
• Current Program Counter (PC) is pushed onto the
• PC is loaded with the interrupt vector 0004h
The ISR determines the source of the interrupt by
polling the Interrupt Flag bits. The Interrupt Flag bits
must be cleared before exiting the ISR to avoid
FIGURE 4-2:
DS41341E-page 44
INSTRUCTION FLOW
event(s)
Enable bit of the interrupt event is contained in the
PIE1 and PIE2 registers)
stack
GIE bit
(INTCON<7>)
INTF flag
(INTCON<1>)
CLKOUT
INT pin
OSC1
Note 1: INTF flag is sampled here (every Q1).
Instruction
Executed
Instruction
Fetched
PC
Operation
2: Asynchronous interrupt latency = 3-4 T
3: CLKOUT is available only in INTOSC and RC Oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in Section 23.0 “Electrical Specifications”.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
(3)
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
Q1
Inst (PC – 1)
Inst (PC)
(1)
INT PIN INTERRUPT TIMING
Q2
PC
(4)
Q3
Q4
(5)
Q1
Inst (PC + 1)
Inst (PC)
Q2
(1)
PC + 1
Q3
CY
. Synchronous latency = 3 T
Q4
Interrupt Latency
Q1
Dummy Cycle
Q2
repeated interrupts. Because the GIE bit is cleared, any
interrupt that occurs while executing the ISR will be
recorded through its Interrupt Flag, but will not cause
the processor to redirect to the interrupt vector.
The RETFIE instruction exits the ISR by popping the
previous address from the stack and setting the GIE bit.
For additional information on a specific interrupt’s
operation, refer to its peripheral chapter.
4.2
Interrupt latency is defined as the time from when the
interrupt event occurs to the time code execution at the
interrupt vector begins. The latency for synchronous
interrupts is 3 instruction cycles. For asynchronous
interrupts, the latency is 3 to 4 instruction cycles,
depending on when the interrupt occurs. See Figure 4-2
for timing details.
PC + 1
—
Note 1: Individual Interrupt Flag bits are set,
Q3
2: All interrupts will be ignored while the GIE
Interrupt Latency
Q4
(2)
CY
regardless of the state of any other
enable bits.
bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.
, where T
Q1
Dummy Cycle
Inst (0004h)
Q2
0004h
CY
= instruction cycle time. Latency
Q3
© 2009 Microchip Technology Inc.
Q4
Q1
Inst (0005h)
Q2
Inst (0004h)
0005h
Q3
Q4
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