ATTINY88-MMU Atmel, ATTINY88-MMU Datasheet - Page 168
ATTINY88-MMU
Manufacturer Part Number
ATTINY88-MMU
Description
MCU AVR 8K FLASH 12MHZ 28-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY88-MMU
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
ATTINY8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
2-Wire, I2S, SPI
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
24
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATQT600, ATAVRTS2080B
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
For Use With
ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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ATtiny48/88
The ADC module contains a prescaler, as illustrated in
ates an acceptable ADC clock frequency from any CPU frequency above 100 kHz. The
prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from the moment
the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as
long as the ADEN bit is set, and is continuously reset when ADEN is low.
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion
starts at the following rising edge of the ADC clock cycle.
A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched
on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry,
as shown in
Figure 17-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conver-
sion and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is
complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conversion
mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new
conversion will be initiated on the first rising ADC clock edge.
Figure 17-5. ADC Timing Diagram, Single Conversion
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
Cycle Number
ADC Clock
ADEN
ADSC
ADIF
ADCH
ADCL
Figure 17-4
1
1
2
MUX and REFS
Update
2
MUX and REFS
Update
below.
12
3
13
Sample & Hold
4
14
5
15
Sample & Hold
6
16
First Conversion
17
7
One Conversion
18
8
19
9
20
Figure 17-3 on page
10
Conversion
21
Complete
11
22
Conversion
Complete
23
12
24
13
25
Sign and MSB of Result
Sign and MSB of Result
167, which gener-
LSB of Result
Next Conversion
1
Next
Conversion
1
LSB of Result
8008G–AVR–04/11
2
2
MUX and REFS
Update
MUX and REFS
Update
3
3
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