ATMEGA48V-10MMH Atmel, ATMEGA48V-10MMH Datasheet - Page 53
![MCU AVR 4KB FLASH 20MHZ 28QFN](/photos/12/32/123209/28m1-vqfn_sml.jpg)
ATMEGA48V-10MMH
Manufacturer Part Number
ATMEGA48V-10MMH
Description
MCU AVR 4KB FLASH 20MHZ 28QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATAVRTS2080B.pdf
(378 pages)
Specifications of ATMEGA48V-10MMH
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
ATMEGA48x
Core
AVR8
3rd Party Development Tools
EWAVR, EWAVR-BL
Data Bus Width
8 bit
Maximum Clock Frequency
10 MHz
Operating Supply Voltage
1.8 V to 5.5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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2545S–AVR–07/10
If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in
the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE
and WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is use-
ful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and
System Reset Mode, WDIE must be set after each interrupt. This should however not be done
within the interrupt service routine itself, as this might compromise the safety-function of the
Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a Sys-
tem Reset will be applied.
Table 10-1.
Note:
• Bit 4 - WDCE: Watchdog Change Enable
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit,
and/or change the prescaler bits, WDCE must be set.
Once written to one, hardware will clear WDCE after four clock cycles.
• Bit 3 - WDE: Watchdog System Reset Enable
WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is
set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during con-
ditions causing failure, and a safe start-up after the failure.
WDTON
1
1
1
1
0
1. WDTON Fuse set to “0“ means programmed and “1“ means unprogrammed.
(1)
Watchdog Timer Configuration
WDE
0
0
1
1
x
WDIE
0
1
0
1
x
Mode
Stopped
Interrupt Mode
System Reset Mode
Interrupt and System Reset
Mode
System Reset Mode
ATmega48/88/168
Action on Time-out
None
Interrupt
Reset
Interrupt, then go to System
Reset Mode
Reset
53
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