ATTINY43U-SUR Atmel, ATTINY43U-SUR Datasheet - Page 79
ATTINY43U-SUR
Manufacturer Part Number
ATTINY43U-SUR
Description
MCU AVR 4KB FLASH 8MHZ 20SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY43U-SU.pdf
(182 pages)
Specifications of ATTINY43U-SUR
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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12. 8-bit Timer/Counter with PWM (Timer/Counter0 and Timer/Counter1)
12.1
12.2
8048B–AVR–03/09
Features
Overview
•
•
•
•
•
•
•
Timer/Counter0 and Timer/Conter1 are general purpose Timer/Counter modules with two inde-
pendent Output Compare Units, each, and with PWM support. They allow accurate program
execution timing (event management) and wave generation.
Register and bit references in this section are written in general form. A lower case “n” replaces
the Timer/Counter number, and a lower case “x” replaces the Output Compare Unit, in this case
Compare Unit A or Compare Unit B. However, when using the register or bit defines in a pro-
gram, the precise form must be used, i.e., TCNT0 for accessing Timer/Counter0 counter value
and so on.
A simplified block diagram of the 8-bit Timer/Counter is shown in
the actual placement of I/O pins, refer to
including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca-
tions are listed in the
Figure 12-1. 8-bit Timer/Counter Block Diagram
Two Independent Output Compare Units
Double Buffered Output Compare Registers
Clear Timer on Compare Match (Auto Reload)
Glitch Free, Phase Correct Pulse Width Modulator (PWM)
Variable PWM Period
Frequency Generator
Six Independent Interrupt Sources (TOV0, OCF0A, OCF0B, TOV1, OCF1A, and OCF1B)
“Register Description” on page
Timer/Counter
TCCRnA
OCRnA
TCNTn
OCRnB
=
=
Direction
Count
Clear
Control Logic
Figure 1-1 on page
TOP
=
TCCRnB
Value
BOTTOM
Fixed
TOP
clk
=
90.
Tn
0
2. CPU accessible I/O Registers,
OCnA
(Int.Req.)
OCnB
(Int.Req.)
TOVn
(Int.Req.)
Clock Select
Generation
Generation
Waveform
Waveform
( From Prescaler )
Detector
Edge
Figure 12-1 on page
OCnA
OCnB
Tn
79. For
79
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