ATTINY48-MMHR Atmel, ATTINY48-MMHR Datasheet - Page 77

• Manufacturer Part Number: ATTINY48-MMHR
• Description: MCU AVR 4KB FLASH 12MHZ 28QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY48-MMHR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.4
10.4.1
10.4.2
8008G–AVR–04/11
Register Description
MCUCR – MCU Control Register
PORTCR – Port Control Register
Table 10-13. Overriding Signals for Alternate Functions in PD[3:0]
• Bit 4 – PUD: Pull-up Disable
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and
PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See
figuring the Pin” on page 61
• Bits 7:4 – BBMx: Break-Before-Make Mode Enable
When these bits are written to one, the port-wise Break-Before-Make mode is activated. The
intermediate tri-state cycle is then inserted when writing DDRxn to make an output. For further
information, see
• Bits 3:0 – PUDx: Port-Wise Pull-up Disable
When these bits are written to one, the port-wise pull-ups in the defined I/O ports are disabled
even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn}
= 0b01). The Port-Wise Pull-up Disable bits are ORed with the global Pull-up Disable bit (PUD)
Bit
0x35 (0x55)
Read/Write
Initial Value
Bit
0x12 (0x32)
Read/Write
Initial Value
Signal
Name
PUOE
PUO
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
PD3/INT1/PCINT19
0
0
0
0
0
0
INT1 ENABLE +
PCINT19 • PCIE2
1
PCINT19 INPUT
INT1 INPUT
–
BBMD
R/W
R
7
–
0
7
0
“Break-Before-Make Switching” on page
BBMC
BPDS
R/W
R/W
6
0
6
0
for more details about this feature.
PD2/INT0/PCINT18
0
0
0
0
0
0
INT0 ENABLE +
PCINT18 • PCIE1
1
PCINT18 INPUT
INT0 INPUT
–
BPDSE
BBMB
R/W
R/W
5
0
5
0
BBMA
PUD
R/W
R/W
4
0
4
0
PUDD
R/W
PD1/PCINT17
0
0
0
0
0
0
PCINT17 • PCIE2
1
PCINT17 INPUT
–
R
3
–
0
3
0
62.
PUDC
R/W
R
2
–
0
2
0
PUDB
R/W
R
1
–
0
1
0
ATtiny48/88
PD0/PCINT16
0
0
0
0
0
0
PCINT16 • PCIE2
1
PCINT16 INPUT
–
PUDA
R/W
R
0
–
0
0
0
PORTCR
MCUCR
“Con-
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