ATTINY48-MMHR Atmel, ATTINY48-MMHR Datasheet - Page 34

• Manufacturer Part Number: ATTINY48-MMHR
• Description: MCU AVR 4KB FLASH 12MHZ 28QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY48-MMHR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.6
6.6.1
6.6.2
34
Register Description
ATtiny48/88
OSCCAL – Oscillator Calibration Register
CLKPR – Clock Prescale Register
The Oscillator Calibration Register is used to trim the internal oscillator to remove process varia-
tions from the oscillator frequency. A pre-programmed calibration value is automatically written
to this register during chip reset, giving the factory calibrated frequency as specified in
1 on page
The application software can write to the OSCCAL register to change the oscillator frequency.
The oscillator can be calibrated to frequencies as specified in
tion outside the given range is not guaranteed.
Note that this oscillator is used to time EEPROM and Flash write accesses, and the write times
will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more than
8.8 MHz. Otherwise, the EEPROM or Flash write may fail.
All register bits are in use for frequency . A setting of 0x00 gives the lowest frequency and a set-
ting of 0xFF gives the highest frequency.
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE
bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is
cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the
CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the
CLKPCE bit.
• Bits 6:4 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal system
clock. These bits can be written run-time to vary the clock frequency to suit the application
requirements. As the divider divides the master clock input to the MCU, the speed of all synchro-
nous peripherals is reduced when a division factor is used. The division factors are given in
Table
The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed,
the CLKPS bits will be reset to 0b0000. If CKDIV8 is programmed, CLKPS bits are reset to
0b0011, giving a division factor of 8 at start up. This feature should be used if the selected clock
source has a higher frequency than the maximum frequency of the device at the present operat-
ing conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8
Fuse setting. The Application software must ensure that a sufficient division factor is chosen if
Bit
(0x66)
Read/Write
Initial Value
Bit
(0x61)
Read/Write
Initial Value
6-6.
208.
CLKPCE
CAL7
R/W
R/W
7
7
0
CAL6
R/W
6
R
6
–
0
CAL5
R/W
5
R
5
–
0
Device Specific Calibration Value
CAL4
R/W
R
4
4
0
–
CLKPS3
CAL3
R/W
R/W
3
3
CLKPS2
See Bit Description
CAL2
R/W
R/W
Table 22-1 on page
2
2
CLKPS1
CAL1
R/W
R/W
1
1
CLKPS0
CAL0
R/W
R/W
0
0
8008G–AVR–04/11
208. Calibra-
Table 22-
OSCCAL
CLKPR