PIC16F688-E/ML Microchip Technology, PIC16F688-E/ML Datasheet - Page 537

• Manufacturer Part Number: PIC16F688-E/ML
• Description: IC PIC MCU FLASH 4KX14 16QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F688-E/ML

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 12
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 16-QFN
• Controller Family/series: PIC16F
• No. Of I/o's: 12
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• No. Of Timers: 2
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART, RS- 232, SCI, USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT16QFN1 - SOCKET TRANSITION 14DIP TO 16QFNAC162061 - HEADER INTRFC MPLAB ICD2 20PINAC162056 - HEADER INTERFACE ICD2 16F688
• Lead Free Status / Rohs Status: Details

1997 Microchip Technology Inc.
BTFSS
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If skip (2nd cycle):
Example 1
Q1
Q1
operation
Case 1:
Case 2:
Decode
No
Q2
Q2
[ label ] BTFSS f,b
0
0
skip if (f<b>) = 1
None
If bit 'b' in register 'f' is '1' then the next instruction is skipped.
If bit 'b' is '1', then the next instruction (fetched during the current instruc-
tion execution) is discarded and a NOP is executed instead, making this a
2 cycle instruction.
1
1(2)
Before Instruction
After Instruction
Before Instruction
After Instruction
register 'f'
operation
HERE
FALSE
TRUE
Read
01
No
f
b < 7
Section 29. Instruction Set
127
PC =
FLAG=
Since FLAG<4>= 0,
PC =
PC =
FLAG=
Since FLAG<4>=1,
PC =
Bit Test f, Skip if Set
BTFSS
GOTO
•
•
•
11bb
Q3
Q3
operation
Process
data
No
addressHERE
xxx0 xxxx
addressFALSE
addressHERE
xxx1 xxxx
addressTRUE
FLAG, 4
PROCESS_CODE
bfff
Q4
Q4
operation
operation
No
No
ffff
DS31029A-page 29-15
29