PIC16F688-I/STG Microchip Technology, PIC16F688-I/STG Datasheet - Page 70
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PIC16F688-I/STG
Manufacturer Part Number
PIC16F688-I/STG
Description
IC PIC MCU FLASH 4KX14 14TSSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(204 pages)
3.PIC16F688T-ISL.pdf
(6 pages)
4.PIC16F688T-ISL.pdf
(4 pages)
5.PIC16F688T-ISL.pdf
(688 pages)
Specifications of PIC16F688-I/STG
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
12
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
14-TSSOP
For Use With
XLT14SS-1 - SOCKET TRANSITION 14DIP/14SSOPAC162061 - HEADER INTRFC MPLAB ICD2 20PINAC162056 - HEADER INTERFACE ICD2 16F688
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F688T-ISL PDF datasheet #3
- PIC16F688T-ISL PDF datasheet #4
- PIC16F688T-ISL PDF datasheet #5
- Current page: 70 of 204
- Download datasheet (4Mb)
PIC16F688
8.1.5
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
Conversion. The ADC interrupt flag is the ADIF bit in
the PIR1 register. The ADC interrupt enable is the ADIE
bit in the PIE1 register. The ADIF bit must be cleared in
software.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP
instruction is always executed. If the user is attempting
to wake-up from Sleep and resume in-line code
execution, the global interrupt must be disabled. If the
global interrupt is enabled, execution will switch to the
Interrupt Service Routine.
Please see Section 8.1.5 “Interrupts” for more
information.
FIGURE 8-3:
DS41203E-page 68
Note:
(ADFM = 0)
(ADFM = 1)
INTERRUPTS
The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
10-BIT A/D CONVERSION RESULT FORMAT
MSB
bit 7
bit 7
Unimplemented: Read as ‘0’
ADRESH
10-bit A/D Result
MSB
bit 0
bit 0
8.1.6
The 10-bit A/D Conversion result can be supplied in
two formats, left justified or right justified. The ADFM bit
of the ADCON0 register controls the output format.
Figure 8-4 shows the two output formats.
bit 7
bit 7
RESULT FORMATTING
10-bit A/D Result
LSB
Unimplemented: Read as ‘0’
© 2009 Microchip Technology Inc.
ADRESL
bit 0
LSB
bit 0
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