PIC12CE518-04I/P Microchip Technology, PIC12CE518-04I/P Datasheet - Page 73

• Manufacturer Part Number: PIC12CE518-04I/P
• Description: IC MCU OTP 512X12 W/EE 8DIP
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12CE518-04I/P

• Core Size: 8-Bit
• Program Memory Size: 768B (512 x 12)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Type: OTP
• Eeprom Size: 16 x 8
• Ram Size: 25 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Controller Family/series: PIC12
• No. Of I/o's: 6
• Eeprom Memory Size: 16Byte
• Ram Memory Size: 25Byte
• Cpu Speed: 4MHz
• No. Of: RoHS Compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: DVA12XP080 - ADAPTER DEVICE FOR MPLAB-ICE
• Data Converters: -
• Connectivity: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4.2
1997 Microchip Technology Inc.
OSC2/CLKOUT
(RC mode)
Clocking Scheme/Instruction Cycle
OSC1
Q4
PC
Q2
Q3
Q1
The clock input (from OSC1) is internally divided by four to generate four non-overlapping
quadrature clocks, namely Q1, Q2, Q3, and Q4. Internally, the program counter (PC) is incre-
mented every Q1, and the instruction is fetched from the program memory and latched into the
instruction register in Q4. The instruction is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow are illustrated in
Example
Figure 4-3: Clock/Instruction Cycle
Q1
Execute INST (PC-1)
Fetch INST (PC)
Q2
T
4-1.
CY
PC
1
Q3
Q4
Q1
Execute INST (PC)
Fetch INST (PC+1)
Section 4. Architecture
Q2
T
PC+1
CY
2
Q3
Q4
Q1
Execute INST (PC+1)
Fetch INST (PC+2)
Q2
T
PC+2
CY
3
Q3
Q4
DS31004A-page 4-5
Figure
Internal
phase
clock
4-3, and
4