PIC12CE518-04I/P Microchip Technology, PIC12CE518-04I/P Datasheet - Page 294
PIC12CE518-04I/P
Manufacturer Part Number
PIC12CE518-04I/P
Description
IC MCU OTP 512X12 W/EE 8DIP
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12C508A-04SM.pdf
(113 pages)
3.PIC12C508A-04SM.pdf
(4 pages)
4.PIC12CE518-04SM.pdf
(16 pages)
Specifications of PIC12CE518-04I/P
Core Size
8-Bit
Program Memory Size
768B (512 x 12)
Oscillator Type
Internal
Core Processor
PIC
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Type
OTP
Eeprom Size
16 x 8
Ram Size
25 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DIP (0.300", 7.62mm)
Controller Family/series
PIC12
No. Of I/o's
6
Eeprom Memory Size
16Byte
Ram Memory Size
25Byte
Cpu Speed
4MHz
No. Of
RoHS Compliant
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
DVA12XP080 - ADAPTER DEVICE FOR MPLAB-ICE
Data Converters
-
Connectivity
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- PIC16F688T-ISL PDF datasheet
- PIC12C508A-04SM PDF datasheet #2
- PIC12C508A-04SM PDF datasheet #3
- PIC12CE518-04SM PDF datasheet #4
- Current page: 294 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
17.4
DS31017A-page 17-18
SSP I
2
C™ Operation
The MSSP module in I
eral call support) and provides interrupts on start and stop bits in hardware to determine a free
bus (multi-master function). The SSP module implements the standard mode specifications as
well as 7-bit and 10-bit addressing.
A “glitch” filter is on the SCL and SDA pins when the pin is an input. This filter operates in both
the 100 KHz and 400 KHz modes. In the 100 KHz mode, when these pins are an output, there
is a slew rate control of the pin that is independent of device frequency.
Figure 17-10: I
Figure 17-11: I
2
2
C Slave Mode Block Diagram
C Master Mode Block Diagram
SDA
SDA
SCL
Baud Rate Generator
2
SCL
SSPADD<6:0>
C mode fully implements all master and slave functions (including gen-
Preliminary
7
Read
Read
Appendix A
clock
clock
shift
shift
MSb
MSb
Start and Stop bit
detect / generate
Stop bit detect
Match detect
SSPBUF reg
Match detect
SSPADD reg
SSPBUF reg
SSPADD reg
SSPSR reg
SSPSR reg
Start and
gives an overview of the I
LSb
LSb
Write
Write
data bus
data bus
Internal
Internal
(SSPSTAT reg)
(SSPSTAT reg)
and Set SSPIF
Set/Clear S bit
Clear/Set P bit
Address Match
Address Match
Set, Reset
S, P bits
and
1997 Microchip Technology Inc.
2
C bus specification.
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