ATTINY13A-MUR Atmel, ATTINY13A-MUR Datasheet - Page 86
![MCU AVR 1KB FLASH 20MHZ 20QFN](/photos/6/87/68751/313-20-qfn_sml.jpg)
ATTINY13A-MUR
Manufacturer Part Number
ATTINY13A-MUR
Description
MCU AVR 1KB FLASH 20MHZ 20QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY13A-SSH.pdf
(176 pages)
Specifications of ATTINY13A-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
1KB (512 x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Lead Free Status / Rohs Status
Details
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86
ATtiny13A
When Auto Triggering is used, the prescaler is reset when the trigger event occurs, as shown in
Figure 14-6
this mode, the sample-and-hold takes place two ADC clock cycles after the rising edge on the
trigger source signal. Three additional CPU clock cycles are used for synchronization logic.
Figure 14-6. ADC Timing Diagram, Auto Triggered Conversion
In Free Running mode, a new conversion will be started immediately after the conversion com-
pletes, while ADSC remains high.
Figure 14-7. ADC Timing Diagram, Free Running Conversion
Cycle Number
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
ADCL
Prescaler
Reset
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
below. This assures a fixed delay from the trigger event to the start of conversion. In
MUX and REFS
Update
1
Conversion
Complete
2
One Conversion
11
3
Sample &
Hold
4
12
5
13
6
7
One Conversion
Next Conversion
1
Sign and MSB of Result
LSB of Result
8
9
2
MUX and REFS
Update
10
Conversion
Complete
3
11
Sample & Hold
12
4
13
Sign and MSB of Result
LSB of Result
8126E–AVR–07/10
Next Conversion
1
Prescaler
Reset
2
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