ATTINY13A-MUR Atmel, ATTINY13A-MUR Datasheet - Page 77
![MCU AVR 1KB FLASH 20MHZ 20QFN](/photos/6/87/68751/313-20-qfn_sml.jpg)
ATTINY13A-MUR
Manufacturer Part Number
ATTINY13A-MUR
Description
MCU AVR 1KB FLASH 20MHZ 20QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY13A-SSH.pdf
(176 pages)
Specifications of ATTINY13A-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
1KB (512 x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Lead Free Status / Rohs Status
Details
- Current page: 77 of 176
- Download datasheet (5Mb)
12. Timer/Counter Prescaler
12.1
12.2
12.3
8126E–AVR–07/10
Overview
Prescaler Reset
External Clock Source
The Timer/Counter can be clocked directly by the system clock (by setting the CSn[2:0] = 1).
This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to
system clock frequency (f
as a clock source. The prescaled clock has a frequency of either f
f
The prescaler is free running, i.e., operates independently of the Clock Select logic of the
Timer/Counter. Since the prescaler is not affected by the Timer/Counter’s clock select, the state
of the prescaler will have implications for situations where a prescaled clock is used. One exam-
ple of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 >
CSn[2:0] > 1). The number of system clock cycles from when the timer is enabled to the first
count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8,
64, 256, or 1024).
It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program
execution.
An external clock source applied to the T0 pin can be used as Timer/Counter clock (clk
T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchro-
nized (sampled) signal is then passed through the edge detector.
a functional equivalent block diagram of the T0 synchronization and edge detector logic. The
registers are clocked at the positive edge of the internal system clock (
parent in the high period of the internal system clock.
The edge detector generates one clk
(CSn[2:0] = 6) edge it detects.
Figure 12-1. T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T0 has been stable for at least one
system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (f
CLK_I/O
Tn
clk
I/O
/256, or f
D
LE
CLK_I/O
Q
/1024.
ExtClk
Synchronization
CLK_I/O
D
< f
clk_I/O
Q
). Alternatively, one of four taps from the prescaler can be used
/2) given a 50/50% duty cycle. Since the edge detector uses
T
0
pulse for each positive (CSn[2:0] = 7) or negative
D
Figure 12-1 on page 77
Q
clk
CLK_I/O
I/O
Edge Detector
). The latch is trans-
/8, f
CLK_I/O
Tn_sync
(To Clock
Select Logic)
T0
shows
). The
/64,
77
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