ATTINY20-CCU Atmel, ATTINY20-CCU Datasheet - Page 14

• Manufacturer Part Number: ATTINY20-CCU
• Description: MCU AVR 2KB FLASH 12MHZ 15UFBGA
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY20-CCU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Package: 15UFBGA
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 12 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 12
• Interface Type: SPI/TWI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 2
• Processor Series: ATtiny
• Core: AVR
• Data Ram Size: 128 B
• Maximum Clock Frequency: 12 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

4.8.3
14
ATtiny20
SREG – Status Register
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter-
rupt enable control is then performed in separate control registers. If the Global Interrupt Enable
Register is cleared, none of the interrupts are enabled independent of the individual interrupt
enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by
the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by
the application with the SEI and CLI instructions, as described in the document “AVR Instruction
Set” and
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti-
nation for the operated bit. A bit from a register in the Register File can be copied into T by the
BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the
BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful
in BCD arithmetic. See document “AVR Instruction Set” and section
on page 210
• Bit 4 – S: Sign Bit, S = N
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement
Overflow Flag V. See document “AVR Instruction Set” and section
page 210
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See document
“AVR Instruction Set” and section
information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See docu-
ment “AVR Instruction Set” and section
information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See document “AVR
Instruction Set” and section
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See document “AVR
Instruction Set” and section
Bit
0x3F
Read/Write
Initial Value
“Instruction Set Summary” on page
for detailed information.
for detailed information.
R/W
7
0
I
R/W
T
6
0
“Instruction Set Summary” on page 210
“Instruction Set Summary” on page 210
⊕
V
R/W
H
5
0
“Instruction Set Summary” on page 210
“Instruction Set Summary” on page 210
R/W
4
S
0
210.
R/W
3
V
0
R/W
N
2
0
“Instruction Set Summary” on
for detailed information.
for detailed information.
“Instruction Set Summary”
R/W
Z
1
0
R/W
C
0
0
8235B–AVR–04/11
for detailed
for detailed
SREG