ATTINY20-MMH Atmel, ATTINY20-MMH Datasheet - Page 85
![MCU AVR 2KB FLASH 12MHZ 20QFN](/photos/30/99/309958/qfn-16_sml.jpg)
ATTINY20-MMH
Manufacturer Part Number
ATTINY20-MMH
Description
MCU AVR 2KB FLASH 12MHZ 20QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY20-EK1.pdf
(224 pages)
Specifications of ATTINY20-MMH
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
ATtiny
Core
AVR
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
SPI, TWI
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY20-MMHR
Manufacturer:
ATMEL
Quantity:
20 000
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12.7
8235B–AVR–04/11
Compare Match Output Unit
pare (1x) strobe bits in Normal mode. The OC1x Register keeps its value even when changing
between Waveform Generation modes.
Be aware that the COM1x[1:0] bits are not double buffered together with the compare value.
Changing the COM1x[1:0] bits will take effect immediately.
The Compare Output Mode (COM1x[1:0]) bits have two functions. The Waveform Generator
uses the COM1x[1:0] bits for defining the Output Compare (OC1x) state at the next compare
match. Secondly the COM1x[1:0] bits control the OC1x pin output source.
simplified schematic of the logic affected by the COM1x[1:0] bit setting. The I/O Registers, I/O
bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control
registers (DDR and PORT) that are affected by the COM1x[1:0] bits are shown. When referring
to the OC1x state, the reference is for the internal OC1x Register, not the OC1x pin. If a system
reset occur, the OC1x Register is reset to “0”.
Figure 12-5. Compare Match Output Unit, Schematic (non-PWM Mode)
The general I/O port function is overridden by the Output Compare (OC1x) from the Waveform
Generator if either of the COM1x[1:0] bits are set. However, the OC1x pin direction (input or out-
put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction
Register bit for the OC1x pin (DDR_OC1x) must be set as output before the OC1x value is visi-
ble on the pin. The port override function is generally independent of the Waveform Generation
mode, but there are some exceptions. See
Table 12-4 on page 100
COMnx1
COMnx0
FOCnx
clk
I/O
Waveform
Generator
for details.
D
D
D
PORT
DDR
OCnx
Table 12-2 on page
Q
Q
Q
99,
1
0
Table 12-3 on page 99
Figure 12-5
ATtiny20
OCnx
shows a
Pin
and
85
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