ATTINY20-MMH Atmel, ATTINY20-MMH Datasheet - Page 135
![MCU AVR 2KB FLASH 12MHZ 20QFN](/photos/30/99/309958/qfn-16_sml.jpg)
ATTINY20-MMH
Manufacturer Part Number
ATTINY20-MMH
Description
MCU AVR 2KB FLASH 12MHZ 20QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY20-EK1.pdf
(224 pages)
Specifications of ATTINY20-MMH
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
ATtiny
Core
AVR
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
SPI, TWI
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY20-MMHR
Manufacturer:
ATMEL
Quantity:
20 000
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- Download datasheet (6Mb)
16.5
16.5.1
8235B–AVR–04/11
Register Description
SPCR – SPI Control Register
Figure 16-4. SPI Transfer Format with CPHA = 1
Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient
time for data signals to stabilize. This is shown in
on page 136
Table 16-2.
• Bit 7 – SPIE: SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if
the Global Interrupt Enable bit in SREG is set.
• Bit 6 – SPE: SPI Enable
When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI
operations.
Bit
0x30
Read/Write
Initial Value
SCK (CPOL = 0)
mode 1
SCK (CPOL = 1)
mode 3
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SPI Mode
SS
MSB first (DORD = 0)
LSB first (DORD = 1)
0
1
2
3
and
SPI Modes
SPIE
R/W
7
0
Table 16-4 on page
Conditions
CPOL=0, CPHA=0
CPOL=0, CPHA=1
CPOL=1, CPHA=0
CPOL=1, CPHA=1
SPE
R/W
6
0
MSB
LSB
DORD
R/W
5
0
Bit 6
Bit 1
136.
MSTR
R/W
4
0
Bit 5
Bit 2
Leading Edge
Sample (Rising)
Setup (Rising)
Sample (Falling)
Setup (Falling)
Table
CPOL
R/W
3
0
Bit 4
Bit 3
16-2, which is a summary of
CPHA
R/W
Bit 3
Bit 4
2
0
SPR1
R/W
Bit 2
Bit 5
1
0
Trailing eDge
Setup (Falling)
Sample (Falling)
Setup (Rising)
Sample (Rising)
ATtiny20
SPR0
R/W
Bit 1
Bit 6
0
0
Table 16-3
LSB
MSB
SPCR
135
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