ATTINY20-SSU Atmel, ATTINY20-SSU Datasheet - Page 138
![no-image](/images/manufacturer_photos/0/0/78/atmel_sml.jpg)
ATTINY20-SSU
Manufacturer Part Number
ATTINY20-SSU
Description
MCU AVR 2KB FLASH 12MHZ 14SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY20-EK1.pdf
(224 pages)
Specifications of ATTINY20-SSU
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
ATtiny
Core
AVR
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
SPI, TWI
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY20-SSU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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- Download datasheet (6Mb)
17. TWI – Two Wire Slave Interface
17.1
17.2
17.3
138
Features
Overview
General TWI Bus Concepts
ATtiny20
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The Two Wire Interface (TWI) is a bi-directional, bus communication interface, which uses only
two wires. The TWI is I
bility with SMBus” on page
A device connected to the bus must act as a master or slave.The master initiates a data transac-
tion by addressing a slave on the bus, and telling whether it wants to transmit or receive data.
One bus can have several masters, and an arbitration process handles priority if two or more
masters try to transmit at the same time.
The TWI module in ATtiny20 implements slave functionality, only. Lost arbitration, errors, colli-
sions and clock holds on the bus are detected in hardware and indicated in separate status
flags.
Both 7-bit and general address call recognition is implemented in hardware. 10-bit addressing is
also supported. A dedicated address mask register can act as a second address match register
or as a mask register for the slave address to match on a range of addresses. The slave logic
continues to operate in all sleep modes, including Power down. This enables the slave to wake
up from sleep on TWI address match. It is possible to disable the address matching and let this
be handled in software instead. This allows the slave to detect and respond to several
addresses. Smart Mode can be enabled to auto trigger operations and reduce software
complexity.
The TWI module includes bus state logic that collects information to detect START and STOP
conditions, bus collision and bus errors. The bus state logic continues to operate in all sleep
modes including Power down.
The Two-Wire Interface (TWI) provides a simple two-wire bi-directional bus consisting of a serial
clock line (SCL) and a serial data line (SDA). The two lines are open collector lines (wired-AND),
and pull-up resistors (Rp) are the only external components needed to drive the bus. The pull-up
resistors will provide a high level on the lines when none of the connected devices are driving
the bus. A constant current source can be used as an alternative to the pull-up resistors.
Phillips I
SMBus compatible (with reservations)
100 kHz and 400 kHz support at low system clock frequencies
Slew-Rate Limited Output Drivers
Input Filter provides noise suppression
7-bit, and General Call Address Recognition in Hardware
Address mask register for address masking or dual address match
10-bit addressing supported
Optional Software Address Recognition Provides Unlimited Number of Slave Addresses
Slave can operate in all sleep modes, including Power Down
Slave Arbitration allows support for SMBus Address Resolve Protocol (ARP)
2
C compatible
2
C compatible and, with reservations, SMBus compatible (see
144).
8235B–AVR–04/11
“Compati-
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