ATTINY5-TS8R Atmel, ATTINY5-TS8R Datasheet - Page 31
ATTINY5-TS8R
Manufacturer Part Number
ATTINY5-TS8R
Description
IC MCU AVR 512B FLASH SOT-23-6
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY9-MAHR.pdf
(169 pages)
Specifications of ATTINY5-TS8R
Package / Case
SOT-23-6
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
12MHz
Number Of I /o
4
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32 x 8
Program Memory Size
512B (512 x 8)
Data Converters
A/D 4x8b
Oscillator Type
Internal
Peripherals
POR, PWM, WDT
Core Size
8-Bit
Processor Series
ATTINY5x
Core
AVR8
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY5-TS8R
Manufacturer:
Atmel
Quantity:
8 105
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8.3.1
8.3.1.1
8.3.1.2
8127D–AVR–02/10
Procedure for Changing the Watchdog Timer Configuration
Safety Level 1
Safety Level 2
To prevent unintentional disabling of the Watchdog or unintentional change of time-out period,
two different safety levels are selected by the fuse WDTON as shown in
See
Table 8-1.
The sequence for changing configuration differs between the two safety levels, as follows:
In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit
to one without any restriction. A special sequence is needed when disabling an enabled Watch-
dog Timer. To disable an enabled Watchdog Timer, the following procedure must be followed:
In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A
protected change is needed when changing the Watchdog Time-out period. To change the
Watchdog Time-out, the following procedure must be followed:
WDTON
Unprogrammed
Programmed
1. Write the signature for change enable of protected I/O registers to register CCP
2. Within four instruction cycles, in the same operation, write WDE and WDP bits
1. Write the signature for change enable of protected I/O registers to register CCP
2. Within four instruction cycles, write the WDP bit. The value written to WDE is irrelevant
“Procedure for Changing the Watchdog Timer Configuration” on page 31
WDT Configuration as a Function of the Fuse Settings of WDTON
Safety
Level
1
2
WDT
Initial State
Disabled
Enabled
How to
Disable the WDT
Protected change
sequence
Always enabled
ATtiny4/5/9/10
How to
Change Time-out
No limitations
Protected change
sequence
Table 8-1 on page
for details.
31.
31
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