ATTINY10-MAHR Atmel, ATTINY10-MAHR Datasheet - Page 39
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ATTINY10-MAHR
Manufacturer Part Number
ATTINY10-MAHR
Description
MCU AVR 1024K FLASH 12MHZ 8UDFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY10-MAHR
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Peripherals
POR, PWM, WDT
Number Of I /o
4
Program Memory Size
1KB (512 x 16)
Program Memory Type
FLASH
Ram Size
32 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Other names
ATTINY10-MAH
ATTINY10-MAH
ATTINY10-MAH
- Current page: 39 of 169
- Download datasheet (5Mb)
9.3.2
9.3.3
8127D–AVR–02/10
EIMSK – External Interrupt Mask Register
EIFR – External Interrupt Flag Register
selected, the low level must be held until the completion of the currently executing instruction to
generate an interrupt.
Table 9-2.
• Bits 7:1 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 0 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-
nal pin interrupt is enabled. The Interrupt Sense Control bits (ISC01 and ISC00) in the External
Interrupt Control Register A (EICRA) define whether the external interrupt is activated on rising
and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt
request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt
Request 0 is executed from the INT0 Interrupt Vector.
• Bits 7:1 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 0 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set
(one). If the I-bit in SREG and the INT0 bit in EIMSK are set (one), the MCU will jump to the cor-
responding Interrupt Vector.
The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared
by writing a logical one to it.
This flag is constantly zero when INT0 is configured as a level interrupt.
Bit
0x13
Read/Write
Initial Value
Bit
0x14
Read/Write
Initial Value
ISC01
0
0
1
1
Interrupt 0 Sense Control
ISC00
R
R
7
–
0
7
–
0
0
1
0
1
Description
The low level of INT0 generates an interrupt request.
Any logical change on INT0 generates an interrupt request.
The falling edge of INT0 generates an interrupt request.
The rising edge of INT0 generates an interrupt request.
R
R
6
–
0
6
–
0
R
R
5
–
0
5
–
0
R
R
4
–
0
4
–
0
R
R
3
–
0
3
–
0
R
R
2
–
0
2
–
0
ATtiny4/5/9/10
R
R
1
–
0
1
–
0
INTF0
INTO
R/W
R/W
0
0
0
0
EIMSK
EIFR
39
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