MCF5484CZP200 Freescale Semiconductor, MCF5484CZP200 Datasheet - Page 12

• Manufacturer Part Number: MCF5484CZP200
• Description: IC MPU 32BIT COLDF 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF548xr

Specifications of MCF5484CZP200

• Core Processor: Coldfire V4E
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 99
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.43 V ~ 1.58 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Program Memory Size: 64KB
• Cpu Speed: 200MHz
• Embedded Interface Type: I2C, UART, DMA
• Digital Ic Case Style: BGA
• No. Of Pins: 388
• Supply Voltage Range: 3V To 3.6V, 1.43V To 1.58V
• Rohs Compliant: No
• For Use With: M5485EVBGHSE - KIT DEV GHS FOR M5485EVBM5485EVBGHS - KIT DEV GHS FOR M5485EVBM5485BFEE - MODULE MCF5485 FIRE ENGINEM5485AFEE - MODULE MCF5485 FIRE ENGINEM5485AFE - MODULE MCF5485 FIRE ENGINEM5484GFEE - MODULE M5484 FIRE ENGINEM5484LITEKITE - KIT DEV FOR MCF548X FAMILY
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Reset Timing Specifications
7
Table 9
Figure 10
8
A multi-function external bus interface called FlexBus is provided on the MCF5482 with basic functionality to interface to
slave-only devices up to a maximum bus frequency of 66 MHz. It can be directly connected to asynchronous or synchronous
devices such as external boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no
additional circuitry. For asynchronous devices, a simple chip-select based interface can be used. The FlexBus interface has six
general purpose chip-selects (FBCS[5:0]). Chip-select FBCS0 can be dedicated to boot ROM access and can be programmed
to be byte (8 bits), word (16 bits), or longword (32 bits) wide. Control signal timing is compatible with common ROM / flash
memories.
12
lists specifications for the reset timing parameters shown in
shows reset timing for the values in
Reset Timing Specifications
FlexBus
Mode Select
1
Num
RSTI and FlexBus data lines are synchronized internally. Setup and hold
times must be met only if recognition on a particular clock is required.
R1
R2
R3
FlexBus
CLKIN
1
RSTI
NOTE:
MCF548x ColdFire
Valid to CLKIN (setup)
CLKIN to invalid (hold)
Mode selects are registered on the rising clock edge before
the cycle in which RSTI is recognized as being negated.
Table 9. Reset Timing Specifications
RSTI to invalid (hold)
RSTI pulse duration
R1
Characteristic
Table
Figure 10. Reset Timing
9.
®
Microprocessor, Rev. 4
R2
Figure 10
50 MHz CLKIN
Min
1.0
1.0
8
5
R1
R3
Max
—
—
—
—
CLKIN cycles
Units
ns
ns
ns
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