MCIMX515CJM6C Freescale Semiconductor, MCIMX515CJM6C Datasheet - Page 81

MULTIMEDIA PROC 529-LFBGA

MCIMX515CJM6C

Manufacturer Part Number
MCIMX515CJM6C
Description
MULTIMEDIA PROC 529-LFBGA
Manufacturer
Freescale Semiconductor
Series
i.MX51r
Datasheets

Specifications of MCIMX515CJM6C

Core Processor
ARM Cortex-A8
Core Size
32-Bit
Speed
600MHz
Connectivity
1-Wire, EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
128
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.8 V ~ 1.15 V
Oscillator Type
External
Operating Temperature
-20°C ~ 85°C
Package / Case
529-LFBGA
Processor Series
i.MX51
Core
ARM Cortex A8
Data Bus Width
32 bit
Program Memory Size
36 KB
Data Ram Size
128 KB
Interface Type
I2C, SPI, SSI, UART, USB
Maximum Clock Frequency
200 MHz
Number Of Timers
5
Operating Supply Voltage
0.8 V to 1.15 V
Maximum Operating Temperature
+ 95 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
MCIMX51EVKJ
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCIMX515CJM6C
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MCIMX515CJM6C
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
MCIMX515CJM6CR2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
4.7.6.2
Figure 47
characteristics.
Freescale Semiconductor
1
IC10 Fall time of SCLH signal
IC12 Fall time of SDAH signal
IC13 Set-up time for STOP condition
IC14 Capacitive load for each bus line (C
IC11 Rise time of SDAH signal
IC1 SCLH cycle time
IC2 Setup time (repeated) START condition
IC3 Hold time (repeated) START condition
IC4 LOW Period of the SCLH Clock
IC5 HIGH Period of SCLH Clock
IC6 Data set-up time
IC7 Data hold time
IC8 Rise time of SCLH
IC9 Rise time of SCLH signal after a repeated START condition and after an acknowledge bit
ID
A device must internally provide a hold time of at least 300 ns for SDAH signal in order to bridge the undefined region of the
falling edge of SCLH.
SDAH
SCLH
depicts the high-speed mode timings of HS-I
IC3
High-Speed Mode Timing Parameters
START
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4
IC9
IC4
Table 76. HS-I
IC6
IC1
IC11
Figure 47. High-Speed Mode Timing
IC5
b
)
IC7
Parameter
2
C High-Speed Mode Timing Parameters
IC10
IC8
IC12
2
C module, and
IC2
START
Table 76
IC13
lists the timing
STOP
Electrical Characteristics
High-Speed Mode
Min
160
160
160
160
10
60
10
10
10
10
10
10
0
1
Max
100
3.4
START
70
40
80
40
80
80
MHz
Unit
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
81

Related parts for MCIMX515CJM6C