HD64F7044F28V Renesas Electronics America, HD64F7044F28V Datasheet - Page 464

• Manufacturer Part Number: HD64F7044F28V
• Description: IC SUPERH MCU FLASH 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7040r

Specifications of HD64F7044F28V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 28.7MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 7 Pipeline Operation
Double-Length Multiply/Accumulate Instruction (SH-2 CPU, SH-DSP): Includes the
following instruction type:
MAC.L
@Rm+, @Rn+
: Slot
Instruction A
IF
ID
EX
MA
MA
mm
mm
mm
mm
Next instruction
IF
—
ID
EX
MA
WB
Third instruction
IF
ID
EX
MA
WB
......
Figure 7.32 Multiply/Accumulate Instruction Pipeline
The pipeline has nine stages: IF, ID, EX, MA, MA, mm, mm, mm, and mm (figure 7.32). The
second MA reads the memory and accesses the multiplier. The mm indicates that the multiplier is
operating. The mm operates for four cycles after the final MA ends, regardless of slot. The ID of
the instruction after the MAC.L instruction is stalled for one slot. The two MAs of the MAC.L
instruction, when they contend with IF, split the slots as described in section 7.2.1, Contention
between Instruction Fetch (IF) and Memory Access (MA).
When an instruction that does not use the multiplier follows the MAC.L instruction, the MAC.L
instruction may be considered to be a five-stage pipeline instruction of IF, ID, EX, MA, MA. In
such cases, the ID of the next instruction simply stalls one slot and thereafter the pipeline operates
normally. When an instruction that uses the multiplier comes after the MAC.L instruction,
contention occurs with the multiplier, so operation is different from normal.
This occurs in the following cases:
1. When a MAC.W instruction is located immediately after another MAC.W instruction
2. When a MAC.L instruction is located immediately after a MAC.W instruction
3. When a MULS.W instruction is located immediately after a MAC.W instruction
4. When a DMULS.L instruction is located immediately after a MAC.W instruction
5. When an STS (register) instruction is located immediately after a MAC.W instruction
6. When an STS.L (memory) instruction is located immediately after a MAC.W instruction
7. When an LDS (register) instruction is located immediately after a MAC.W instruction
8. When an LDS.L (memory) instruction is located immediately after a MAC.W instruction
Rev. 5.00 Jun 30, 2004 page 448 of 512
REJ09B0171-0500O