MCIMX515DJM8C Freescale Semiconductor, MCIMX515DJM8C Datasheet - Page 77

• Manufacturer Part Number: MCIMX515DJM8C
• Description: MULTIMEDIA PROC 529-LFBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX51r

Specifications of MCIMX515DJM8C

• Core Processor: ARM Cortex-A8
• Core Size: 32-Bit
• Speed: 800MHz
• Connectivity: 1-Wire, EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 128
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.8 V ~ 1.15 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 529-LFBGA
• Processor Series: i.MX51
• Core: ARM Cortex A8
• Data Bus Width: 32 bit
• Program Memory Size: 36 KB
• Data Ram Size: 128 KB
• Interface Type: I2C, SPI, SSI, UART, USB
• Maximum Clock Frequency: 200 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 0.8 V to 1.15 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: MCIMX51EVKJ
• Minimum Operating Temperature: - 20 C
• Cpu Speed: 800MHz
• Digital Ic Case Style: BGA
• Supply Voltage Range: 0.8V To 1.15V
• Operating Temperature Range: -20°C To +85°C
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.7.4.2
The MII transmit signal timing affects the FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, and
FEC_TX_CLK signals. The transmitter functions correctly up to a FEC_TX_CLK maximum frequency
of 25 MHz + 1%. There is no minimum frequency requirement. In addition, the processor clock frequency
must exceed twice the FEC_TX_CLK frequency.
and
Freescale Semiconductor
1
.
FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing in 10 Mbps 7-wire interface mode.
Num
M5
M6
M7
M8
Figure 43
FEC_TXD[3:0] (outputs)
FEC_RXD[3:0] (inputs)
FEC_RX_CLK (input)
FEC_TX_CLK (input)
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER invalid
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER valid
FEC_TX_CLK pulse width high
FEC_TX_CLK pulse width low
MII Transmit Signal Timing
shows MII transmit signal timing diagram for the values listed in
FEC_RX_ER
FEC_RX_DV
FEC_TX_EN
FEC_TX_ER
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4
Figure 43. MII Transmit Signal Timing Diagram
Figure 42. MII Receive Signal Timing Diagram
Characteristic
Table 71. MII Transmit Signal Timing
M1
1
M5
M2
Table 71
M6
M3
M7
lists MII transmit channel timing parameters
35%
35%
Min
—
M4
5
M8
Max
65%
65%
Table
20
—
Electrical Characteristics
71.
FEC_TX_CLK period
FEC_TX_CLK period
Unit
ns
ns
77