MCIMX515DJM8C Freescale Semiconductor, MCIMX515DJM8C Datasheet - Page 68

• Manufacturer Part Number: MCIMX515DJM8C
• Description: MULTIMEDIA PROC 529-LFBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX51r

Specifications of MCIMX515DJM8C

• Core Processor: ARM Cortex-A8
• Core Size: 32-Bit
• Speed: 800MHz
• Connectivity: 1-Wire, EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 128
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.8 V ~ 1.15 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 529-LFBGA
• Processor Series: i.MX51
• Core: ARM Cortex A8
• Data Bus Width: 32 bit
• Program Memory Size: 36 KB
• Data Ram Size: 128 KB
• Interface Type: I2C, SPI, SSI, UART, USB
• Maximum Clock Frequency: 200 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 0.8 V to 1.15 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: MCIMX51EVKJ
• Minimum Operating Temperature: - 20 C
• Cpu Speed: 800MHz
• Digital Ic Case Style: BGA
• Supply Voltage Range: 0.8V To 1.15V
• Operating Temperature Range: -20°C To +85°C
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Electrical Characteristics
Figure 35
appear in
68
1
2
DDR17
DDR18
DDR17
DDR18
DDR19
DDR20
DDR21
DDR22
DDR23
These values are for DQ/DM slew rates of 1 V/ns and DQS/DQS_B differential slew rates of 2 V/ns. For different values use
derating table below
These values are for DQ/DM slew rates of 1 V/ns and DQS slew rates of 1 V/ns. For different values use derating table below
ID
Table
DQM (output)
shows the timing diagram for DDR2 SDRM write cycle. The timing parameters for this diagram
DQS (output)
DQ and DQM setup time to DQS (differential strobe)
DQ and DQM hold time to DQS (differential strobe)
DQ and DQM setup time to DQS (single-ended strobe)
DQ and DQM hold time to DQS
Write cycle DQS falling edge to SDCLK output setup time
Write cycle DQS falling edge to SDCLK output hold time
DQS latching rising transitions to associated clock edges
DQS high level width
DQS low level width
DQ (output)
SDCLK_B
SDCLK
60.
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4
DDR17
DDR21
DDR17
Figure 35. DDR2 SDRAM Write Cycle
Table 60. DDR2 SDRAM Write Cycle
Parameter
(single-ended strobe)
Data
DM
DDR18
DDR18
Data
DM
DDR17
DDR17
1
Data
DM
1
2
DDR22
2
Data
DM
DDR23
DDR18
DDR18
Data
DM
t
t
Symbol
t
t
DH1(base)
DS1(base)
DS(base)
DH(base)
t
t
t
t
t
DQSS
DQSH
DQSL
DSS
DSH
Data
DM
DDR19
SDCLK = 200 MHz
0.275
0.025
0.025
–0.25
0.15
0.35
0.35
Min
0.2
0.2
Freescale Semiconductor
Data
DM
Max
0.25
Data
DM
—
—
—
—
—
—
—
—
DDR20
Unit
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns